DS80C310 datasheet(12/23 Pages) DALLAS

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DS80C310

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3. Idle mode current is measured with a 33 MHz clock source driving XTAL1, VCC =5.5V, RST at

ground, all other pins disconnected.

4. Stop mode current measured with XTAL1 and RST grounded, VCC =5.5V, all other pins

disconnected.

5. When addressing external memory.

6. RST=VCC. This condition mimics operation of pins in I/O mode.

7. During a 0 to 1 transition, a one-shot drives the ports hard for two clock cycles. This measurement

reflects port in transition mode.

8. Ports 1 and 3 source transition current when being pulled down externally. It reaches its maximum at

approximately 2V.

9. 0.45<VIN <VCC. Not a high- impedance input. This port is a weak address holding latch because Port 0

is dedicated as an address bus on the DS80C310. Peak current occurs near the input transition point of

the latch, approximately 2V.

10. Current required from external circuit to hold a logic low level on an I/O pin while the corresponding

port latch bit is set to 1. This is only the current required to hold the low level; transitions from 1 to 0

on an I/O pin will also have to overcome the transition current.

TYPICAL ICC VERSUS FREQUENCY Figure 2

DS80C310 数据表(PDF) 12 Page - Dallas Semiconductor