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EM260-RTR 数据表(PDF) 6 Page - Silicon image

部件名 EM260-RTR
功能描述  ZigBee/802.15.4 Network Processor
PDF  50 Pages
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制造商  SILICONIMAGE [Silicon image]
网页  http://www.siliconimage.com
标志 SILICONIMAGE - Silicon image

EM260-RTR 数据表(HTML) 6 Page - Silicon image

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EM260
120-0260-000M Rev 1.1
Page 6
Pin #
Signal
Directio
n
Description
24
VDD_PADS
Power
Pads supply (2.1 – 3.6V)
25
N.C.
I
When using the SPI interface, this signal is left not connected.
TXD
O
UART Transmitted Data (from EM260 to Host)
26
nHOST_INT
O
SPI Host Interrupt signal (from EM260 to Host)
RXD
I
UART Received Data (from Host to EM260)
27
SIF_CLK
I
Programming and Debug Interface, Clock (internal pull down)
28
SIF_MISO
O
Programming and Debug Interface, Master In / Slave Out
29
SIF_MOSI
I
Programming and Debug Interface, Master Out / Slave In (external pull-down
required to guarantee state in Deep Sleep Mode)
30
nSIF_LOAD
I/O
Programming and Debug Interface, load strobe (open collector with internal pull up)
31
GND
Power
Ground Supply
32
VDD_FLASH
Power
1.8V Flash memory supply; should be connected to VREG_OUT
33
SDBG
O
Spare Debug signal
34
LINK_ACTIVITY
O
Link and Activity signal
35
nWAKE
I
SPI Wake Interrupt signal (from Host to EM260)
N.C.
I
When using the UART interface, this signal is left not connected.
36
VDD_CORE
Power
1.8V digital core supply; should be connected to VREG_OUT
37
VDD_SYNTH_PRE
Power
1.8V synthesizer and prescalar supply; should be connected to VREG_OUT
38
OSCB
I/O
24MHz crystal oscillator or left open for when using an external clock input on OSCA
39
OSCA
I/O
24MHz crystal oscillator or external clock input
40
VDD_24MHZ
Power
1.8V high-frequency oscillator supply; should be connected to VREG_OUT
41
GND
Ground
Ground supply pad in the bottom center of the package forms Pin 41 (see the EM260
Reference Design for PCB considerations)



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