TSB41AB2IPAP datasheet(23/55 Pages) TI1

23 / 55 page

TSB41AB2, TSB41AB2I

IEEE 1394a2000 TWOPORT CABLE

TRANSCEIVER/ARBITER

SLLS424G − JUNE 2000 − REVISED DECEMBER 2004

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

APPLICATION INFORMATION

Table 2. Base Register Field Descriptions (Continued)

FIELD

SIZE

TYPE

DESCRIPTION

RPIE

Rd/Wr

Resuming port interrupt enable. This bit, if set to 1, enables the port event interrupt (PEI) bit to be set

whenever resume operations begin on any port. This bit also enables the C/LKON output signal to be

activated whenever the LLC is inactive and any of the CTOI, CPSI, or STOI interrupt bits are set. This bit is

reset to 0 by hardware reset and is unaffected by bus reset.

ISBR

Rd/Wr

Initiate short arbitrated bus reset. This bit, if set to 1, instructs the PHY to initiate a short (1.3

µs) arbitrated

bus reset at the next opportunity. This bit is reset to 0 by bus reset.

NOTE: Legacy IEEE Std 1394-1995 compliant PHYs may not be capable of performing short bus resets.

Therefore, initiation of a short bus reset in a network that contains such a legacy device results in a long bus

reset being performed.

CTOI

Rd/Wr

Configuration time-out interrupt. This bit is set to 1 when the arbitration controller times out during tree-ID

start, and may indicate that the bus is configured in a loop. This bit is reset to 0 by hardware reset, or by writing

a 1 to this register bit.

If the CTOI and RPIE bits are both set and the LLC is or becomes inactive, the PHY activates the C/LKON

output to notify the LLC to service the interrupt.

NOTE: If the network is configured in a loop, only those nodes that are part of the loop generate a

configuration time-out interrupt. All other nodes instead time out waiting for the tree-ID and/or self-ID process

to complete and then generate a state time-out interrupt and bus reset.

CPSI

Rd/Wr

Cable power status interrupt. This bit is set to 1 whenever the CPS input transitions from high to low indicating

that cable power may be too low for reliable operation. This bit is reset to 1 by hardware reset. It can be

cleared by writing a 1 to this register bit.

If the CPSI and RPIE bits are both set and the LLC is or becomes inactive, the PHY activates the C/LKON

output to notify the LLC to service the interrupt.

STOI

Rd/Wr

State time-out interrupt. This bit indicates that a state time-out has occurred (which also causes a bus reset

to occur). This bit is reset to 0 by hardware reset, or by writing a 1 to this register bit. If the STOI and RPIE

bits are both set and the LLC is or becomes inactive, the PHY activates the C/LKON output to notify the LLC

to service the interrupt.

PEI

Rd/Wr

Port event interrupt. This bit is set to 1 upon a change in the bias, connected, disabled, or fault bits for any

port for which the port interrupt enable (PIE) bit is set. Additionally, if the resuming port interrupt enable (RPIE)

bit is set, the PEI bit is set to 1 at the start of resume operations on any port. This bit is reset to 0 by hardware

reset, or by writing a 1 to this register bit.

If the PEI bit is set (regardless of the state of the RPEI bit) and the LLC is or becomes inactive, the PHY

activates the C/LKON output to notify the LLC to service the interrupt.

EAA

Rd/Wr

Enable accelerated arbitration. This bit enables the PHY to perform the various arbitration acceleration

enhancements defined in IEEE 1394a-2000 (ACK-accelerated arbitration, asynchronous fly-by

concatenation, and isochronous fly-by concatenation). This bit is reset to 0 by hardware reset and is

unaffected by bus reset.

NOTE: The EAA bit should be set only if the attached LLC is IEEE 1394a-2000 compliant. If the LLC is not

IEEE 1394a-2000 compliant, use of the arbitration acceleration enhancements may interfere with

isochronous traffic by excessively delaying the transmission of cycle-start packets.

EMC

Rd/Wr

Enable multispeed concatenated packets. This bit enables the PHY to transmit concatenated packets of

differing speeds in accordance with the protocols defined in IEEE 1394a-2000. This bit is reset to 0 by

hardware reset and is unaffected by bus reset.

NOTE: The use of multispeed concatenation is completely compatible with networks containing legacy IEEE

Std 1394-1995 PHYs. However, use of multispeed concatenation requires that the attached LLC be IEEE

1394a-2000 compliant.

Page_Select

Rd/Wr

Page select. This field selects the register page to use when accessing register addresses 8 through 15. This

field is reset to 0 by hardware reset and is unaffected by bus reset.

Port_Select

Rd/Wr

Port select. This field selects the port when accessing per-port status or control (for example, when one of

the port status/control registers is accessed in page 0). Ports are numbered starting at 0. This field is reset

to 0 by hardware reset and is unaffected by bus reset.

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