TSB41AB2IPAP datasheet(38/55 Pages) TI1

38 / 55 page

TSB41AB2, TSB41AB2I

IEEE 1394a2000 TWOPORT CABLE

TRANSCEIVER/ARBITER

SLLS424G − JUNE 2000 − REVISED DECEMBER 2004

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

receive (continued)

It is possible for the PHY to receive a null packet, which consists of the data-prefix state on the serial bus followed

by the data-end state, without any packet data. A null packet is transmitted whenever the packet speed exceeds

the capability of the receiving PHY, or whenever the LLC immediately releases the bus without transmitting any

data. In this case, the PHY asserts receive on the CTL terminals with the data-on indication (all 1s) on the D

terminals, followed by idle on the CTL terminals, without any speed code or data being transferred. In all cases,

the TSB41AB2 sends at least one data-on indication before sending the speed code or terminating the receive

operation.

The TSB41AB2 also transfers its own self-ID packet, transmitted during the self-ID phase of bus initialization,

to the LLC. This packet is transferred to the LLC just as any other received self-ID packet. Figure 18 is the

reception timing diagram for normal packets, and Figure 19 is the reception timing diagram for null packets.

SPD

(1)

(5)

(4)

(2)

(3)

FF (Data-On)

D0–D7

CTL0, CTL1

SYSCLK

Figure 18. Normal Packet Reception Timing

The sequence of events for a normal packet reception is as follows:

Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL lines.

Normally, the interface is Idle until receive is asserted. However, the receive operation may interrupt a status

transfer operation that is in progress so that the CTL lines may change from status to receive without an

intervening idle.

Data-on indication. The PHY asserts the data-on indication code on the D lines for one or more cycles

preceding the speed code.

Speed code. The PHY indicates the speed of the received packet by asserting a speed code on the D lines

for one cycle immediately preceding packet data. The link decodes the speed code on the first receive cycle

for which the D lines are not the data-on code. If the speed code is invalid, or indicates a speed higher than

that which the link is capable of handling, the link should ignore the subsequent data.

Receive data. Following the data-on indication (if any) and the speed code, the PHY asserts packet data

on the D lines with receive on the CTL lines for the remainder of the receive operation.

Receive operation terminated. The PHY terminates the receive operation by asserting idle on the CTL lines.

The PHY asserts at least one cycle of idle following a receive operation.

(1)

(2)

(3)

FF (Data-On)

D0–D7

CTL0, CTL1

SYSCLK

Figure 19. Null Packet Reception Timing

TSB41AB2IPAP 数据表(PDF) 38 Page - Texas Instruments

TSB41AB2IPAP 数据表(HTML) 38 Page - Texas Instruments

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