TSB41AB2IPAP datasheet(43/55 Pages) TI1

43 / 55 page

TSB41AB2, TSB41AB2I

IEEE 1394a2000 TWOPORT CABLE

TRANSCEIVER/ARBITER

SLLS424G − JUNE 2000 − REVISED DECEMBER 2004

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

interface reset and disable (continued)

The sequence of events for resetting the PHY-LLC interface when it is in the differentiated mode of operation

(ISO terminal is low) is as follows:

Normal operation. Interface is operating normally, with LPS active, SYSCLK active, status and packet data

reception and transmission via the CTL and D lines, and request activity via the LREQ line.

LPS deasserted. The LLC deasserts the LPS signal and, within 1

µs, terminates any request or interface

bus activity, and places its LREQ, CTL, and D outputs into a high-impedance state (the LLC should

terminate any output signal activity such that signals end in a logic 0 state).

Interface reset. After TLPS_RESET time, the PHY determines that LPS is inactive, terminates any interface

bus activity, and places its CTL and D outputs into a high-impedance state (the PHY terminates any output

signal activity such that signals end in a logic 0 state). The PHY-LLC interface is now in the reset state.

Interface restored. After the minimum TRESTORE time, the LLC may again assert LPS active. (The minimum

TRESTORE interval provides sufficient time for the biasing networks used in Annex J type isolation barrier

circuits to stabilize and reach a quiescent state if the isolation barrier has somehow become unbalanced.)

When LPS is asserted, the interface is initialized.

LPS

CTL0, CTL1

LREQ

SYSCLK

(3)

(2)

(1)

D0−D7

(high)

(4)

TLPS_RESET

TRESTORE

ISO

Figure 23. Interface Reset, ISO High

The sequence of events for resetting the PHY-LLC interface when it is in the nondifferentiated mode of operation

(ISO terminal is high) is as follows:

Normal operation. Interface is operating normally, with LPS asserted, SYSCLK active, status and packet

data reception and transmission via the CTL and D lines, and request activity via the LREQ line. In

Figure 23, the LPS signal is shown as a nonpulsed level signal. However, it is permissible to use a pulsed

signal for LPS in a direct connection between the PHY and LLC; a pulsed signal is required when using an

isolation barrier (whether of the TI bus-holder type or Annex J type).

LPS deasserted. The LLC deasserts the LPS signal and, within 1

µs, terminates any request or interface

bus activity, places its CTL and D outputs into a high-impedance state, and drives its LREQ output low.

Interface reset. After TLPS_RESET time, the PHY determines that LPS is inactive, terminates any interface

bus activity, and drives its CTL and D outputs low. The PHY-LLC interface is now in the reset state.

Interface restored. After the minimum TRESTORE time, the LLC may again assert LPS active. When LPS

is asserted, the interface is initialized.

TSB41AB2IPAP 数据表(PDF) 43 Page - Texas Instruments

TSB41AB2IPAP 数据表(HTML) 43 Page - Texas Instruments

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