TSB41AB2IPAP datasheet(33/55 Pages) TI1

33 / 55 page

TSB41AB2, TSB41AB2I

IEEE 1394a2000 TWOPORT CABLE

TRANSCEIVER/ARBITER

SLLS424G − JUNE 2000 − REVISED DECEMBER 2004

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

output differentiation (continued)

The TSB41AB2 implements differentiation circuitry functionally equivalent to that shown in Figure 15 on the

bidirectional CTL0 – CTL1and D0 – D7 terminals. The TSB41AB2 also implements an input hysteresis buffer on

the LREQ input to convert this signal to the correct logic level when differentiated. The LLC must also implement

similar output differentiation and input hysteresis circuitry on its CTL and D terminals, and output differentiation

circuitry on its LREQ terminal.

3-State Output

Driver

Input Buffer With

Hysteresis

DIN

DOUT

ISO

OUTEN

INIT

SYSCLK

To/From

Internal

Device Logic

D Terminal

Figure 15. Input/Output Differentiation Logic

LLC service request

To request access to the bus, to read or write a PHY register, or to control arbitration acceleration, the LLC sends

a serial bit stream on the LREQ terminal as shown in Figure 16.

LR(n-2)

LR3

LR2

LR1

LR0

LR(n-1)

NOTE: Each cell represents one clock sample time, and n is the number of bits in the request stream.

Figure 16. LREQ Request Stream

The length of the stream varies depending on the type of request as shown in Table 12.

Table 12. Request Stream Bit Length

REQUEST TYPE

NUMBER OF BITS

Bus request

7 or 8

Read register request

Write register request

Acceleration control request

TSB41AB2IPAP 数据表(PDF) 33 Page - Texas Instruments

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