TSB41AB2IPAP datasheet(35/55 Pages) TI1

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TSB41AB2, TSB41AB2I

IEEE 1394a2000 TWOPORT CABLE

TRANSCEIVER/ARBITER

SLLS424G − JUNE 2000 − REVISED DECEMBER 2004

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

LLC service request (continued)

For a read register request the length of the LREQ bit stream is 9 bits as shown in Table 16.

Table 16. Read Register Request

BIT(S)

NAME

DESCRIPTION

Start bit

Indicates the beginning of the transfer (always 1)

1− 3

Request type

A 100 indicating this is a read register request

4− 7

Address

Identifies the address of the PHY register to be read

Stop bit

Indicates the end of the transfer (always 0)

For a write register request the length of the LREQ bit stream is 17 bits as shown in Table 17.

Table 17. Write Register Request

BIT(S)

NAME

DESCRIPTION

Start bit

Indicates the beginning of the transfer (always 1)

1− 3

Request type

A 101 indicating this is a write register request

4− 7

Address

Identifies the address of the PHY register to be written to

8−15

Data

Gives the data that is to be written to the specified register address

For an acceleration control request the length of the LREQ bit stream is 6 bits as shown in Table 18.

Table 18. Acceleration Control Request

BIT(S)

NAME

DESCRIPTION

Start bit

Indicates the beginning of the transfer (always 1)

1− 3

Request type

A 110 indicating this is an acceleration control request

Control

Asynchronous period arbitration acceleration is enabled if 1, and disabled if 0.

Stop bit

Indicates the end of the transfer (always 0)

For fair or priority access, the LLC sends the bus request (FairReq or PriReq) at least one clock after the

PHY-LLC interface becomes idle. If the CTL terminals are asserted receive (10b) by the PHY, then any pending

fair or priority request is lost (cleared). Additionally, the PHY ignores any fair or priority requests if receive is

asserted while the LLC is sending the request. The LLC may then reissue the request one clock after the next

interface idle.

The cycle master node uses a priority bus request (PriReq) to send a cycle start message. After receiving or

transmitting a cycle start message, the LLC can issue an isochronous bus request (IsoReq). The PHY clears

an isochronous request only when the serial bus has been won.

To send an acknowledge packet, the LLC must issue an immediate bus request (ImmReq) during the reception

of the packet addressed to it. This is required in order to minimize the idle gap between the end of the received

packet and the start of the transmitted acknowledge packet. As soon as the receive packet ends, the PHY

immediately grants control of the bus to the LLC. The LLC sends an acknowledgment to the sender unless the

header CRC of the received packet is corrupted. In this case, the LLC does not transmit an acknowledge, but

instead cancels the transmit operation and releases the interface immediately; the LLC must not use this grant

to send another type of packet. After the interface is released the LLC may proceed with another request.

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