TLV2553

SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002

17

www.ti.com

PARAMETER MEASUREMENT INFORMATION

timing diagrams

1

2

3

5

4

6

10

11

12

1

MSB–1 MSB–2 MSB–3 MSB–4 MSB–5

MSB–8 MSB–9

LSB+1

LSB

Hi–Z State

2

3

D6

D5

D4

D3

D2

D1

D0

D6

D5

D7

8

7

9

MSB–6 MSB–7

D7

Previous Conversion Data

MSB

MSB

MSB–2

MSB–1

Shift in New Multiplexer Address,

Simultaneously Shift Out Previous Conversion Result

Access

Cycle

Sample Cycle

Channel

Address

A/D Conversion Interval

Output Data

Format

tCONV

CS

I/O

CLOCK

DATA

OUT

DATA

IN

EOC

Initialize

Initialize

Figure 33. Timing for 12-Clock Transfer Using CS With DATA OUT Set for MSB First

MSB

1

2

3

5

4

610

11

12

1

MSB–1 MSB–2 MSB–3 MSB–4 MSB–5

MSB–8 MSB–9 LSB+1

LSB

2

3

D6

D5

8

7

9

MSB–6 MSB–7

D7

Low Level

MSB

D6

D5

D4

D3

D2

D1

D0

D7

MSB–2

MSB–1

Shift in New Multiplexer Address,

Simultaneously Shift Out Previous Conversion Result

Access

Cycle

Sample Cycle

Channel

Address

A/D Conversion Interval

Output Data

Format

tCONV

Previous Conversion Data

CS

I/O

CLOCK

DATA

OUT

DATA IN

EOC

Initialize

Initialize

Figure 34. Timing for 12-Clock Transfer Not Using CS With DATA OUT Set for MSB First

NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after the CS falling edge before responding to

control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.