TLV2553

SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002

22

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PRINCIPLES OF OPERATION

Table 2. Command Set (CMR) and Configuration

SDI D[7:4]

Binary,

HEX

COMMAND

0000b

0001b

0010b

0011b

0100b

0101b

0110b

0111b

1000b

1001b

1010b

1011b

1100b

1101b

1110b

1111b

0h

1h

2h

3h

4h

5h

6h

7h

8h

9h

Ah

Bh

Ch

Dh

Eh

Fh

SELECT analog input channel 0

SELECT analog input channel 1

SELECT analog input channel 2

SELECT analog input channel 3

SELECT analog input channel 4

SELECT analog input channel 5

SELECT analog input channel 6

SELECT analog input channel 7

SELECT analog input channel 8

SELECT analog input channel 9

SELECT analog input channel 10

SELECT TEST,

Voltage = (VREF+ + VREF–)/2

SELECT TEST, Voltage = REFM

SELECT TEST, Voltage = REFP

SW POWERDOWN (analog + reference)

Reserved

CONFIGURATION

CFGR1

SDI

D[3:0]

D[3:2]

D1

D0

01: 8-bit output length

X0: 12-bit output length (see Note)

11: 16-bit output length

0: MSB out first

1: LSB out first

0: Unipolar binary

1: Bipolar 2s complement

NOTE: Select 12-bit output mode to achieve 200 KSPS

sampling rate.

data input—address/command bits

The four MSBs (D7–D4) of the input data register are the address or command. These can be used to address

one of the 11 input channels, address one of three reference-test voltages, or activate software power-down

mode. All address/command bits affect the current conversion, which is the conversion that immediately follows

the current I/O cycle. They also have access to CFGR1 except for command 1111b, which is reserved.

data output length

CFGR1 bits (D3 and D2) of the data register select the output data length. The data-length selection is valid

for the current I/O cycle (the cycle in which the data is read). The data-length selection, being valid for the current

I/O cycle, allows device start-up without losing I/O synchronization. A data length of 8, 12, or 16 bits can be

selected. Since the converter has 12-bit resolution, a data length of 12 bits is suggested.

With D3 and D2 set to 00 or 10, the device is in the 12-bit data-length mode and the result of the current

conversion is output as a 12-bit serial data stream during the next I/O cycle. The current I/O cycle must be exactly

12 bits long for proper synchronization, even when this means corrupting the output data from a previous

conversion. The current conversion is started immediately after the twelfth falling edge of the current I/O cycle.

With bits D3 and D2 set to 11, the 16-bit data-length mode is selected, which allows convenient communication

with 16-bit serial interfaces. In the 16-bit mode, the result of the current conversion is output as a 16-bit serial

data stream during the next I/O cycle with the four LSBs always reset to 0 (pad bits). The current I/O cycle must

be exactly 16 bits long to maintain synchronization even when this means corrupting the output data from the

previous conversion. The current conversion is started immediately after the sixteenth falling edge of the current

I/O cycle.