TLV2553

SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002

24

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PRINCIPLES OF OPERATION

C1

0.1

µF

Decoupling Cap

GND

Analog

Supply

Sample

∼50 pF

CDAC

Convert

REF+

REF–

VCC

Figure 39. Reference Block

EOC output

Pin 19 outputs the status of the ADC conversion. When programmed as EOC, the output indicates the beginning

and the end of conversion. In the reset state, EOC is always high. During the sampling period (beginning after

the fourth falling edge of the I/O CLOCK sequence), EOC remains high until the internal sampling switch of the

converter is safely opened. The opening of the sampling switch occurs after the eighth, twelfth, or sixteenth I/O

CLOCK falling edge, depending on the data-length selection in the input data register. After the EOC signal goes

low, the analog input signal can be changed without affecting the conversion result.

The EOC signal goes high again after the conversion is completed and the conversion result is latched into the

output data register. The rising edge of EOC returns the converter to a reset state and a new I/O cycle begins.

On the rising edge of EOC, the first bit of the current conversion result is on DATA OUT when CS is low. When

CS is toggled between conversions, the first bit of the current conversion result occurs on DATA OUT at the

falling edge of CS.

chip-select input (CS)

CS enables and disables the device. During normal operation, CS should be low. Although the use of CS is not

necessary to synchronize a data transfer, it can be brought high between conversions to coordinate the data

transfer of several devices sharing the same bus.

When CS is brought high, the serial-data output is immediately brought to the high-impedance state, releasing

its output data line to other devices that may share it. After an internally generated debounce time, I/O CLOCK

is inhibited, thus preventing any further change in the internal state.

When CS is subsequently brought low again, the device is reset. CS must be held low for an internal debounce

time before the reset operation takes effect. After CS is debounced low, I/O CLOCK must remain inactive (low)

for a minimum time before a new I/O cycle can start.