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TLV2553 数据表(PDF) 6 Page - Texas Instruments |
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TLV2553 数据表(HTML) 6 Page - Texas Instruments |
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6 / 30 page ![]() TLV2553 SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002 6 www.ti.com external reference specifications PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT Reference input voltage REF VCC = 4.5 V to 5.5 V –0.1 0 0.1 V Reference input voltage, REF– VCC = 2.7 V to 3.6 V –0.1 0 0.1 V Reference input voltage REF+ VCC = 4.5 V to 5.5 V 2 VCC V Reference input voltage, REF+ VCC = 2.7 V to 3.6 V 2 VCC V External reference input voltage difference, VCC = 4.5 V to 5.5 V 1.9 VCC V g, (REF+) – (REF–) VCC = 2.7 V to 3.6 V 1.9 VCC V External reference supply current CS at 0 V VCC = 4.5 V to 5.5 V 0.94 mA External reference supply current CS at 0 V VCC = 2.7 V to 3.6 V 0.62 mA VCC =5V Static 1 M Ω Reference input impedance VCC = 5 V During sampling/conversion 6 9 k Ω Reference input impedance VCC =2 7V Static 1 M Ω VCC = 2.7 V During sampling/conversion 6 9 k Ω † All typical values are at TA = 25°C. NOTE: Add a 0.1- µF capacitor between REF+ and REF– pins when external reference is used. operating characteristics over recommended operating free-air temperature range, VREF+ = 5 V, I/O CLOCK frequency = 15 MHz when VCC = 5 V, VREF+ = 2.5 V, I/O CLOCK frequency = 10 MHz when VCC = 2.7 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT INL Integral linearity error (see Note 3) –1 1 LSB DNL Differential linearity error –1 1 LSB EO Offset error (see Note 4) See Note 2 –2 2 mV EG Gain error (see Note 4) See Note 2 –3 3 mV ET Total unadjusted error (see Note 5) ±1.5 LSB Address data input = 1011 2048 Self-test output code (see Table 2 and Note 6) Address data input = 1100 0 Address data input = 1101 4095 † All typical values are at TA = 25°C. NOTES: 2. Analog input voltages greater than the voltage applied to REF+ convert as all ones (111111111111), while input voltages less than the voltage applied to REF– convert as all zeros (000000000000). 3. Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics. 4. Gain error is the difference between the actual midstep value and the nominal midstep value in the transfer diagram at the specified gain point after the offset error has been adjusted to zero. Offset error is the difference between the actual midstep value and the nominal midstep value at the offset point. 5. Total unadjusted error comprises linearity, zero-scale, and full-scale errors. 6. Both the input address and the output codes are expressed in positive logic. |
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