TLV2553

SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002

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PRINCIPLES OF OPERATION

conversion cycle

A conversion cycle is started only after the I/O cycle is completed, which minimizes the influence of external

digital noise on the accuracy of the conversion. This cycle is transparent to the user because it is controlled by

an internal clock (oscillator). The total conversion time is equal to 13.5 OSC clocks plus a small delay (~25 ns)

to start the OSC. During the conversion period, the device performs a successive-approximation conversion

on the analog input voltage.

EOC goes low at the start of the conversion cycle and goes high when the conversion is complete and the output

data register is latched. After EOC goes low, the analog input can be changed without affecting the conversion

result. Since the delay from the falling edge of the last I/O CLOCK to the falling edge of EOC is fixed, any

time-varying analog input signals can be digitized at a fixed rate without introducing systematic harmonic

distortion or noise due to timing uncertainty.

power up and initialization

After power up, CS must be taken from high to low to begin an I/O cycle. The EOC pin is initially high, and the

configuration register is set to all zeroes. The contents of the output data register are random, and the first

conversion result should be ignored. To initialize during operation, CS is taken high and is then returned low

to begin the next I/O cycle. The first conversion after the device has returned from the power-down state may

not read accurately due to internal device settling.

Table 1. Operational Terminology

Current (N) I/O cycle

The entire I/O CLOCK sequence that transfers address and control data into the data register and clocks

the digital result from the previous conversion from DATA OUT

Current (N) conversion cycle

The conversion cycle starts immediately after the current I/O cycle. The end of the current I/O cycle is the

last clock falling edge in the I/O CLOCK sequence. The current conversion result is loaded into the out-

put register when conversion is complete.

Current (N) conversion result

The current conversion result is serially shifted out on the next I/O cycle.

Previous (N–1) conversion cycle

The conversion cycle just prior to the current I/O cycle

Next (N+1) I/O cycle

The I/O period that follows the current conversion cycle

Example:

In 12-bit mode, the result of the current conversion cycle is a 12-bit serial-data stream clocked out during the

next I/O cycle. The current I/O cycle must be exactly 12 bits long to maintain synchronization, even when this

corrupts the output data from the previous conversion. The current conversion is begun immediately after the

twelfth falling edge of the current I/O cycle.

data input

The data input is internally connected to an 8-bit serial-input address and control register. The register defines

the operation of the converter and the output data length. The host provides the input data byte with the MSB

first. Each data bit is clocked in on the rising edge of the I/O CLOCK sequence (see Table 2 for the data

input-register format).