AS3709 datasheet(57/74 Pages) AMSCO

57 / 74 page

ams Datasheet, Confidential: 2013-Aug [1-02]

AS3709 – 57

Reg i st er Description

Figure 76:

ReferenceControl Register (Address 35h)

Addr: 35h

ReferenceControl

Bit

Bit Name

Default

Access

Bit Description

7on_reset_delay

Sets the on reset delay time

0 : 8 sec (if onkey_reset=1)

1 : 4 sec (if onkey_reset=1)

clk_div2

Divide internal clock oscillator by 2 to reduce

quiescent current for low power operation

0 : Normal mode

1 : Internal clock frequency divided by two. All

timings are increased by two. Switching frequency of

all DCDC converters are divided by two. Reduced

transient performance of DCDC converters.

standby_mode

_on

0RW

Setting to 1 sets the PMU into standby mode. All

regulators are disabled except those regulators

enabled by register Reg standby mode. XRES will be

pulled to low. A normal startup of all regulators will be

done with any interrupt (has to be enabled before

entering standby mode). During this startup,

regulators defined by Reg standby mode register are

continuously on.

3:1

clk_int

'b000

Sets the internal CLK frequency fCLK used for fuel

gauge, DCDCs, PWM, ...

0 : 4 MHz (default)

1 : 3.8 MHz

2 : 3.6 MHz

3 : 3.4 MHz

4 : 3.2 MHz

5 : 3.0 MHz

6 : 2.8 MHz

7 : 2.6 MHz

All frequencies, timings and delays in this datasheet

are based on 4MHz clk_int

low_power_on

Enable low power mode of internal reference.

0 : Standard mode

1 : Low power mode - all specification except noise

parameters are still valid. Iq reduced by approx. 30μA

AS3709 数据表(PDF) 57 Page - ams AG

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