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AS3709 数据表(PDF) 60 Page - ams AG

部件名 AS3709
功能描述  關PMIC with 5 DCDC and 2 LDOs
PDF  74 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  AMSCO [ams AG]
网页  http://www.ams.com
标志 AMSCO - ams AG

AS3709 数据表(HTML) 60 Page - ams AG

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AS3709 – 60
ams Datasheet, Confidential: 2013-Aug [1-02]
Re g i st e r De sc rip t ion
Figure 80:
RegStatus Register (Address 73h)
Figure 81:
InterruptMask1 Register (Address 74h)
Addr: 73h
RegStatus
Bit
Bit Name
Default
Access
Bit Description
7:5
-
‘b000
N/A
Do not use
4sd5_lv
0
RO
Bit is set when voltage of SD5 drops below low voltage
threshold (-5%) (1msec debounce time default)
3sd4_lv
0
RO
Bit is set when voltage of SD4 drops below low voltage
threshold (-5%) (1msec debounce time default)
2sd3_lv
0
RO
Bit is set when voltage of SD3 drops below low voltage
threshold (-5%) (1msec debounce time default)
1sd2_lv
0
RO
Bit is set when voltage of SD2 drops below low voltage
threshold (-5%) (1msec debounce time default)
0sd1_lv
0
RO
Bit is set when voltage of SD1 drops below low voltage
threshold (-5%) (1msec debounce time default)
Addr: 74h
InterruptMask1
Bit
Bit Name
Default
Access
Bit Description
7
LowVsup_int_m
1
RW
Set to 0 to enable the interrupt
6
ovtmp_int_m
1
RW
Set to 0 to enable the interrupt
5
onkey_int_m
1
RW
Set to 0 to enable the interrupt
4
sd5_lv_int_m
1
RW
Set to 0 to enable the interrupt
3
sd4_lv_int_m
1
RW
Set to 0 to enable the interrupt
2
sd3_lv_int_m
1
RW
Set to 0 to enable the interrupt
1
sd2_lv_int_m
1
RW
Set to 0 to enable the interrupt
0
sd1_lv_int_m
1
RW
Set to 0 to enable the interrupt



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