GMS90C320

OCT. 2000 Ver 1.2

15

Timer/Counter0and1

Timer/Counter 0 and 1 can be used in four operating modes as listed in Table 4:

In the “timer” function (C/T = “0”) the register is incremented every machine cycle. Therefore the count rate is

.

In the “counter” function the register is incremented in response to a 1-to-0 transition at its corresponding external input pin

(P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a falling edge the max. count rate is

. External inputs

INT0 and INT1 (P3.2, P3.3) can be programmed to function as a gate to facilitate pulse width measurements.

Figure 2 illustrates the input clock logic.

Figure 2 Timer/Counter 0 and 1 Input Clock Logic

Table 4

Timer/Counter 0 and 1 Operating Modes

Mode

Description

TMOD

Input Clock

GATE

C/T

M1

M0

Internal

External

(Max.)

0

8-bit timer/counter with a

divide-by-32 prescaler

XX

0

0

1

16-bit timer/counter

XX

0

1

2

8-bit timer/counter with 8-bit

autoreload

XX

1

0

3

Timer/counter 0 used as one

8-bit timer/counter and one 8-

bit timer

Timer 1 stops

XX

1

1

ƒ

OSC

12

32

×

-------------------

ƒ

OSC

24

32

×

-------------------

ƒ

OSC

12

----------------

ƒ

OSC

24

----------------

ƒ

OSC

12

----------------

ƒ

OSC

24

----------------

ƒ

OSC

12

----------------

ƒ

OSC

24

----------------

ƒ

OSC

12

⁄

ƒ

OSC

24

⁄

÷12

C/T

TMOD

0

1

GATE

TMOD

TR 0/1

TCON

P3.4/T0

P3.5/T1

P3.2/INT0

P3.3/INT1

Timer 0/1

Input Clock

Control

ƒ

⁄