ICS1523

MDS 1523 Y

14

Revision 110905

Integrated Circuit Systems

525 Race Street, San Jose, CA 95126

tel (408) 297-1201

www.icst.com

Section 12 Timing Diagrams

Figure 12-1 DPA Operation

DPA Offset = CLK Period * (# of DPA Elements Selected [0x4:4~0]

(# of DPA Elements Available)[0x5:1-0]

Table 12-1 DPA Offset Ranges

Using the DPA above 160 MHz is not recommended. Set DPA_OS = 0 for speeds in excess of 160 MHz to bypass

the DPA. The DPA Resolution Select register (0x5:0~1) is double-buffered. Working registers are loaded only after

a DPA Software reset (0x8=xA)

Register 5

0x4:5-0

Maximum

DPA Clock Range in MHz

1~0

Total # of DPA

Elements

Selected #

of DPA

Elements

Min

Max

00

16

0F

48

160

01

32

1F

24

80

11

64

3F

12

40

HSYNC

DPA Offset when

DPA_OS [5-0] = 0

.

.

.

One full speed clock period

DPA Offset when

DPA_OS [5-0] = 1

DPA Offset when

DPA_OS [5-0] = 2

DPA Offset when

DPA_OS [5-0] = Max

1 unit of DPA delay

2 units of DPA delay

Maximum units of DPA delay

Fixed delay

− See Figure 12-2 and Figure 12-3

1 unit of DPA delay