MDS 1523 Y

7

Revision 110905

Integrated Circuit Systems

525 Race Street, San Jose, CA 95126

tel (408) 297-1201

www.icst.com

ICS1523

4.1 Register Set Summary (continued)

Reg.

Index

Name

Access

Bit Name

Bit #

Reset

Value

Description

Notes

0x6

Output

Enables

R / W

OE_Pck

0

0

Output Enable for PECL CLK (Pins 20, 21)

0=High Z, 1=Enabled

OE_Tck

1

0

Output Enable for STTL_3 CLK (Pin 17)

0=High Z, 1=Enabled

OE_P2

2

0

Output Enable for PECL CLK/2 (Pins 22, 23)

0=High Z, 1=Enabled

OE_T2

3

0

Output Enable for STTL_3 CLK/2 (Pin 16)

0=High Z, 1=Enabled)

OE_F

4

0

Output Enable for STTL_3 FUNC Output (Pin15)

0=High Z, 1=Enabled

Ck2_Inv

5

0

CLK/2 Invert (0=Not Inverted, 1= Inverted)

Out_Scl

6-7

0

CLK Scaler (pin 17)

Bit 7, 6 = (00 = ÷ 1, 01 = ÷ 2, 10 = ÷ 4, 11 = ÷ 8)

See Section 5, “Register Set Details”

0x7

Osc_Div

R / W

Osc_Div

0-6

0-6

0

Osc Divider modulus

See Section 6, “OSC Divider and REF”

In-Sel

7

1

Input Select

0=HSYNC Input, 1=Osc Divider

0x8

Reset

Write

DPA

0-3

x

Writing xAh resets DPA and loads working 0x5

PLL

4-7

x

Writing 5xh resets PLL and loads working 0x1- 0x3

0x10

Chip Ver

Read

Chip Ver

0-7

17

Chip Version 23 Dec (17h) as in 1523

0x11

Chip Rev

Read

Chip Rev

0-7

01

Initial value 01h. Value Increments with each all-layer change.

0x12

Rd_Reg

Read

Reserved

0

N/A

Reserved

PLL_Lock

1

N/A

PLL Lock Status

0=Unlocked, 1=Locked

Reserved

2-7

0

Reserved