ICS1523MLF datasheet(3/21 Pages) ICST

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Video Clock Synthesizer with I2C Programmable Delay

MDS 1523 Y

Revision 110905

Integrated Circuit Systems

525 Race Street, San Jose, CA 95126

tel (408) 297-1201

www.icst.com

ICS1523

MHz even if a low output frequency is required.The

output of the VCOD is the full speed output frequency

seen on the CLK pins.

1.7 Dynamic Phase Adjust (DPA)

The VCOD output clock is then sent through the DPA

for phase adjustment relative to the input HSYNC as

well as the 12-bit internal Feedback Divider. An

external divider may alternately be used and it’s output

must be input on the EXTFB pin. The feedback divider

controls how many clocks are seen during every cycle

of the input reference.

The DPA allows a programmable delay between the

input HSYNC to the clock and FUNC outputs, relative

to the input HSYNC signal on a sub-pixel basis. A delay

of up to one clock period is programmable: See Note 6

in Section 5, “Register Set Details” for more

information.

1.8 Feedback Divider (FD) and FUNC

The 12-bit FD controls how many clocks are seen

between successive HSYNCs.

The number of clocks per HSYNC is FB + 8

The FD output is a 4 CLK wide, active high signal

called FUNC. The FUNC signal is aligned with the

output clocks via the DPA and is intended to be used by

the system as a replacement for the HSYNC input,

which is of in-determinate quality and is not aligned

with the output clocks. Alternately, the post

Schmitt-trigger HSYNC signal can also be DPA

delayed and then output on the FUNC pin. See 0x0:5.

1.9 Phase Frequency Detector (PFD)

The PFD compares the FUNC signal to the selected

input described below and controls the filter voltage by

enabling and disabling the charge pump. The charge

pump has programmable current drive and will source

and sink current as appropriate to keep the input and

the FUNC output aligned.

1.10 HSYNC and REF Inputs

One of the PFDs two possible inputs is HSYNC (pin 7).

HSYNC is conditioned by a high-performance

Schmitt-trigger. This preconditioned HSYNC signal,

called REF, is provided as a reference signal with a

short transition time. REF can be output on pin 14.

1.11 OSC Input

The high-frequency OSC input pin, has a 7-bit user

programmable divider. OSC can also be selected as

the loop input, allowing the loop to operate from any

appropriate, single-ended source, typically a crystal

oscillator.

1.12 FUNC Output

Either the conditioned HSYNC input or the loop output

(recovered HSYNC) is available at the FUNC pin, and

is aligned with the output clocks.

1.13 Logic Inputs

The ICS1523 uses Low-Voltage TTL (LVTTL) inputs

that are 5 volt tolerant such as most VESA compliant

HSYNC and VSYNC signals.

1.14 Output Drivers

The ICS1523 also has SSTL_3 (EIA/JESD8-8) and

low-voltage PECL (Positive ECL) outputs, operating off

the 3.3 V supply voltage.

The SSTL_3 and differential PECL output drivers drive

resistive terminations or transmission lines. At lower

clock frequencies, the SSTL_3 outputs can be

operated unterminated. See Section 9, “Output

Termination”

1.15 Power-On Reset Detection (POR)

The ICS1523 has automatic POR circuitry, meaning it

resets itself if the supply voltage drops below a

threshold values of approximately 1.8 V. No external

connection to a reset signal is required.

1.16 I2C Bus Serial Interface

The ICS1523 uses a 5 V tolerant, industry-standard

I2C-bus serial interface that runs at either low speed

(100 kHz) or high speed (400 kHz). The interface uses

12 indexed registers: one write-only, eight read/write,

and three read-only registers.

Two ICS1523 devices can be addressed according to

the state of the I2CADR pin. When this pin is low the

read address is 4Dh and the write address is 4Ch.

When the pin is high, the read address is 4Fh and the

write address is 4Eh. See Section 11, “Programming”.

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