ICS1523MLF datasheet(4/21 Pages) ICST

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Video Clock Synthesizer with I2C Programmable Delay

MDS 1523 Y

Revision 110905

Integrated Circuit Systems

525 Race Street, San Jose, CA 95126

tel (408) 297-1201

www.icst.com

ICS1523

Section 2 Pin Descriptions

Note 1: These LVTTL inputs are 5 V-tolerant.

Note 2: Connect to ground if unused.

NO.

PIN NAME

TYPE

DESCRIPTION

COMMENTS

Notes

VDDD

POWER

Digital supply

3.3 V to digital sections

VSSD

POWER

Digital ground

SDA

IN/OUT

Serial data

I2C-bus Data

SCL

Serial clock

I2C-bus Clock

COAST

Charge pump enable

Enables\Disables the charge pump

EXTFB

External feedback in

External feedback divider input

HSYNC

Horizontal sync

Clock input to PLL

EXTFIL

External filter

External loop filter

XFILRET

External filter return

External loop filter return

VDDA

POWER

Analog supply

3.3 V for analog circuitry

VSSA

POWER

Analog ground

Ground for analog circuitry

OSC

Oscillator

Input from oscillator or other high

frequency input

1 & 2

I2CADR

I2C address

Chip I2C address select

Low = 4Dh read, 4Ch write

High = 4Fh read, 4Eh write

LOCK/REF

SSTL_3 OUT Lock / Reference

REF (Schmitt conditioned HSYNC) or

PLL lock output

FUNC

SSTL_3 OUT Function output

Output selectable between a 4 clock

wide, active high HSYNC-like output,

and a Schmitt-trigger filtered HSYNC

CLK/2

SSTL_3 OUT Pixel clock/2 output

Output driver for half speed clock

CLK

SSTL_3 OUT Pixel clock output

Output driver for full speed clock

VDDQ

POWER

Output driver supply

3.3 V to output drivers

VSSQ

POWER

Output driver ground

Ground for output drivers

CLK–

OD OUT

Pixel clock outputs

PECL driver for full-speed clock

CLK+

CLK/2–

OD OUT

Pixel clock/2 outputs

PECL driver for half-speed clock

CLK/2+

IREF

Reference current

Reference current for PECL outputs

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