Pin Configuration

SEL0/CLK

1

16

PD

SEL1/DATA

2

15

EXTSEL

VDD

3

14

INIT1

OE

4

13

VDD

GND

5

12

INIT0

X1

6

11

EXTCLK

X2

7

10

FPMODE

MCLK

8

9

VCLK

Pin Descriptions

PIN NUMBER

PIN NAME

DESCRIPTION

1

SEL0-CLK

Clock input in serial programming mode.

Clock select pin in operating mode.

2

SEL1-DATA

Data input in serial programming mode.

Clock select pin in operating mode.

3

AVDD

Power.

4

OE

Tristates outputs when low.

5

GND

Ground.

6

X1

Crystal input.

7

X2

Crystal output.

8

MCLK

Memory clock output.

9

VCLK

Video clock output.

10

FPMODE

Clock select input used to force REG2 programmed frequency.

11

EXTCLK

External clock input.

12

INIT0

Selects initial power-up conditions, LSB.

13

VDD

Power.

14

INIT1

Selects initial power-up conditions, MSB.

15

EXTSEL

Selects external clock input (EXTCLK) as VCLK output.

16

PD

Power-down pin, active low.

16-Pin PDIP or SOIC

ICS82C404

2