Power Management Issues

Power-down mode 1

The ICS82C404 contains a mechanism to reduce the quiescent

power when stand-by operation is desired. Power-down mode

1 is invoked by pulling PD low and having the proper CNTL

register bit set to zero. In this mode, VCOs are shut down, the

VCLK output is forced high, and the MCLK output is set to a

user-defined low frequency value to refresh dynamic RAM.

The power-down MCLK value is determined by the following

equation:

The power-down register divisor is determined according to

the 4-bit word programmed into the PWRDWN register (see

table below).

Power-down Mode 2

When there is no need for any output during power-down, an

alternate mode is available which will completely shut down

all outputs and the reference oscillator, but still preserves all

register contents. Power-down mode 2 is invoked by the first

programming the power-down bit in the CNTL register and

then pulling the PD pin low.

The PD pin

The PD pin has a standard internal pull-up resistor during

normal operation. When the chip goes into power-down mode

1 or 2, the normal pull-up resistor is dynamically switched to

a weak pull-up, which reduces power consumption. If the PD

pin is allowed to float after it has been pulled down, the weak

pull-up will bring the signal high and allow the device to

resume operation.

Power-Down Register Table

PWRDWN bits

PWRDWN

Register Value

Power-down

Divisor

P3

P2

P1

P0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

4

5

6

7

8 (default)

9

A

B

C

D

E

F

n/a

32

30

28

26

24

22

20

18

16

14

12

10

8

6

4

n/a

447.4 kHz

477.3 kHz

511.4 kHz

550.7 kHz

596.6 kHz

650.8 kHz

715.9 kHz

795.5 kHz

894.9 kHz

1.02 MHz

1.19 MHz

1.43 MHz

1.79 MHz

2.39 MHz

3.58 MHz

ICS82C404

7