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ICS82C404 数据表(PDF) 9 Page - Integrated Circuit Systems

部件名 ICS82C404
功能描述  Dual Programmable Graphics Frequency Generator
PDF  13 Pages
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制造商  ICST [Integrated Circuit Systems]
网页  http://www.icst.com
标志 ICST - Integrated Circuit Systems

ICS82C404 数据表(HTML) 9 Page - Integrated Circuit Systems

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Electrical Characteristics (continued)
AC Characteristics
DESCRIPTION
NAME
SYMBOL
MIN
TYP
MAX
UNITS
Reference oscillator value (Note 1)
Reference
frequency
fREF
1
14.31818
60
MHz
1/fREF
Reference period
tREF
16.6
1000
ns
Duty cycle for the input oscillator
defined as t1/tREF
Input duty cycle
t1
25%
75%
Output oscillator values
Output clock
periods
t2
8.33
(120 MHz)
2564
(390 kHz)
ns
Duty cycle for the output oscillators
(Note 2)
Output duty cycle
t3
45%
55%
Rise time for the output oscillators
into a 25pF load
Rise times
t4
3
ns
Fall time for the output oscillators
into a 25pF load
Fall times
t5
3
ns
Old frequency output
freq1 output
tfreq1
New frequency output
freq2 output
tfreq2
Time clock output remains high while
output muxes to reference frequency
fREF mux time
tA
0.5
tREF
1.5
tREF
ns
Interval for serial programming and
for VCO changes to settle (Note 3)
Time-out interval
ttime-out
25
10
ms
Time clock output remains high while
output muxes to new frequency value
tfreq2muxtime
tB
0.5
tREF
1.5
tREF
ns
Time for the output oscillators to go
into tristate mode after OUTDIS-
signal assertion
Tristate
t6
12
ns
Time for the output oscillators to
recover from tristate mode after
OUTDIS-signal goes high
CLK valid
t7
12
ns
Time for power-down mode of
operation to take effect
Power-Down
t8
12
ns
Time for recovery from power-down
mode to a valid CLK
Power-Up
t9
12
ns
Time for MCLK to go high after
PWRDWN is asserted high
MCLKOUT high
t10
0tPWRDWN
ns
Delay of MCLK prior to fMCLK
signal at output
MCLKOUT delay
t11
0.5
tMCLK
1.5
tMCLK
ns
Clock period of serial clock
tserclk
2
tREF
2ms
Set-up time
tSU
20
ns
Hold time
tHD
10
ns
Load command
tldcmd
0t1+30
ns
Notes:
1.
For reference frequencies other than 14.81818 MHz, the pre-loaded ROM frequencies will shift proportionally.
2.
Duty cycle is measured at CMOS threshold levels. At 5 volts, VTH=2.5 volts.
3.
If the interval is too short, see the time-out interval section in the control register definition.
ICS82C404
9



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