AD7853_15 datasheet(19/34 Pages) AD

19 / 34 page

REV. B

–19–

AD7853/AD7853L

Table VI. Power Management Options

PMGT1 PMGT0

SLEEP

Bit

Comment

Full Power-Down if Not Cali-

brating or Converting (Default

Condition After Power-On)

Normal Operation

(Independent of the

SLEEP Pin)

Full Power-Down

Partial Power-Down if Not

Converting

POWER-UP TIMES

Using an External Reference

When the AD7853 is powered up, the part is powered up from

one of two conditions. First, when the power supplies are ini-

tially powered up and, secondly, when the part is powered up

from either a hardware or software power-down (see last section).

When AVDD and DVDD are powered up, the AD7853 should be

left idle for approximately 32 ms (4 MHz CLK) to allow for the

autocalibration if a 10 nF cap is placed on the

CAL pin, (see

Calibration section). During power-up the functionality of the

SLEEP pin is disabled, i.e., the part will not power down until

the end of the calibration if

SLEEP is tied logic low. The auto-

calibration on power-up can be disabled if the

CAL pin is tied to

a logic high. If the autocalibration is disabled, then the user must

take into account the time required by the AD7853 to power-up

before a self-calibration is carried out. This power-up time is the

time taken for the AD7853 to power up when power is first

applied (300

µs) typ) or the time it takes the external reference

to settle to the 12-bit level–whichever is the longer.

The AD7853 powers up from a full hardware or software

power-down in 5

µs typ. This limits the throughput which the

part is capable of to 104 kSPS for the AD7853 operating with a

4 MHz CLK and 66 kSPS for the AD7853L with a 1.8 MHz

CLK when powering down between conversions. Figure 24

shows how power-down between conversions is implemented

using the

CONVST pin. The user first selects the power-down

between conversions option by using the

SLEEP pin and the

power management bits, PMGT1 and PMGT0, in the control

cally enters a full power-down at the end of a conversion, i.e.,

when BUSY goes low. The falling edge of the next

CONVST

pulse causes the part to power up. Assuming the external refer-

ence is left powered up, the AD7853 should be ready for normal

operation 5

µs after this falling edge. The rising edge of CONVST

initiates a conversion so the

CONVST pulse should be at least

µs wide. The part automatically powers down on completion

of the conversion.

NOTE: Where the software CONVST is used or automatic

full power-down, the part must be powered up in software with

an extra write setting PMGT1 = 0 and PMGT0 = 1 before a

conversion is initiated in the next write. Automatic partial power-

down after a calibration is not possible; the part must be powered

down manually. If software calibrations are to be used when

operating in the partial power-down mode, then three separate

writes are required. The first initiates the type of calibration

required, the second write powers the part down into partial

power-down mode, while the third write powers the part up

again before the next calibration command is issued.

5 s

tCONVERT

POWER-UP

TIME

NORMAL

OPERATION

FULL

POWER-DOWN

POWER-UP

TIME

START CONVERSION ON RISING EDGE

POWER-UP ON FALLING EDGE

CONVST

BUSY

Figure 24. Power-Up Timing When Using

CONVST Pin

Using the Internal (On-Chip) Reference

As in the case of an external reference, the AD7853 can power-

up from one of two conditions, power-up after the supplies are

connected or power-up from hardware/software power-down.

When using the on-chip reference and powering up when AVDD

and DVDD are first connected, it is recommended that the power-

up calibration mode be disabled as explained above. When using

the on-chip reference, the power-up time is effectively the time

it takes to charge up the external capacitor on the REFIN/REFOUT

pin. This time is given by the equation:

tUP = 9 × R × C

where R

≅ 150 kΩ and C = external capacitor.

The recommended value of the external capacitor is 100 nF;

this gives a power-up time of approximately 135 ms before a

calibration is initiated and normal operation should commence.

When CREF is fully charged, the power-up time from a hardware

or software power-down reduces to 5

µs. This is because an

internal switch opens to provide a high impedance discharge

path for the reference capacitor during power-down—see Figure

23. An added advantage of the low charge leakage from the

reference capacitor during power-down is that even though the

reference is being powered down between conversions, the

reference capacitor holds the reference voltage to within

0.5 LSBs with throughput rates of 100 samples/second and over

with a full power-down between conversions. A high input im-

pedance op amp like the AD707 should be used to buffer this

reference capacitor if it is being used externally. Note, if the

AD7853 is left in its power-down state for more than 100 ms,

the charge on CREF will start to leak away and the power-up

time will increase. If this long power-up time is a problem, the

user can use a partial power-down for the last conversion so the

reference remains powered up.

AD7853

REFIN/REFOUT

EXTERNAL

CAPACITOR

SWITCH OPENS

DURING POWER-DOWN

BUF

ON-CHIP

REFERENCE

TO OTHER

CIRCUITRY

Figure 25. On-Chip Reference During Power-Down

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