AD7853_15 datasheet(21/34 Pages) AD

21 / 34 page

REV. B

–21–

AD7853/AD7853L

capacitors, one of which is trimmed when an offset or gain cali-

bration is performed. Again it is the ratio of these capacitors to

the capacitors in the DAC that is critical and the calibration

algorithm ensures that this ratio is at a specified value for both

the offset and gain calibrations.

In Bipolar Mode the midscale error is adjusted for an offset

calibration and the positive full-scale error is adjusted for the

gain calibration; in Unipolar Mode the zero-scale error is ad-

justed for an offset calibration and the positive full-scale error is

adjusted for a gain calibration.

Self-Calibration Timing

The diagram of Figure 27 shows the timing for a full self-

calibration. Here the BUSY line stays high for the full length of

the self-calibration. A self-calibration is initiated by bringing the

CAL pin low (which initiates an internal reset) and then high

again or by writing to the control register and setting the STCAL

bit to 1 (note that if the part is in a power-down mode, the

CAL

pulsewidth must take account of the power-up time). The BUSY line

is triggered high from the rising edge of

CAL (or the end of the

write to the control register if calibration is initiated in soft-

ware), and BUSY will go low when the full self-calibration is

complete after a time tCAL as shown in Figure 27.

t1 = 100ns MIN,

t15 = 2.5 tCLKIN MAX,

tCAL = 125013 tCLKIN

(I/P)

BUSY (O/P)

t15

tCAL

Figure 27. Timing Diagram for Full Self-Calibration

For the self-(gain + offset), self-offset and self-gain calibrations,

the BUSY line will be triggered high by the rising edge of the

CAL signal (or the end of the write to the control register if

calibration is initiated in software) and will stay high for the full

duration of the self-calibration. The length of time that the

BUSY is high for will depend on the type of self-calibration that

is initiated. Typical figures are given in Table IX. The timing

diagrams for the other self-calibration options will be similar to

that outlined in Figure 27.

System Calibration Description

System calibration allows the user to take out system errors

external to the AD7853/AD7853L as well as calibrate the errors

of the AD7853/AD7853L itself. The maximum calibration

range for the system offset errors is

±5% of V

REF and for the

system gain errors is

±2.5% of V

REF. This means that the maxi-

mum allowable system offset voltage applied between the

AIN(+) and AIN(–) pins for the calibration to adjust out this

error is

±0.05 × V

REF (i.e., the AIN(+) can be 0.05 × VREF above

AIN(–) or 0.05

× V

REF below AIN(–)). For the system gain error

the maximum allowable system full-scale voltage, in unipolar

mode, that can be applied between AIN(+) and AIN(–) for the

calibration to adjust out this error is VREF

± 0.025 × V

REF (i.e.,

the AIN(+) can be VREF + 0.025

× V

REF above AIN(–) or VREF –

0.025

× V

REF above AIN(–)). If the system offset or system gain

errors are outside the ranges mentioned, the system calibration

algorithm will reduce the errors as much as the trim range allows.

Figures 33 through 35 illustrate why a specific type of system

calibration might be used. Figure 33 shows a system offset cali-

bration (assuming a positive offset) where the analog input

range has been shifted upwards by the system offset after the

system offset calibration is completed. A negative offset may

also be accounted for by a system offset calibration.

MAX SYSTEM FULL SCALE

2.5% FROM VREF

ANALOG

INPUT

RANGE

VREF – 1LSB

SYS OFFSET

AGND

VREF + SYS OFFSET

MAX SYSTEM OFFSET

5% OF VREF

ANALOG

INPUT

RANGE

VREF – 1LSB

SYS OFFSET

AGND

SYSTEM OFFSET

CALIBRATION

MAX SYSTEM OFFSET

5% OF VREF

Figure 28. System Offset Calibration

Figure 29 shows a system gain calibration (assuming a system

full scale greater than the reference voltage) where the analog

input range has been increased after the system gain calibration

is completed. A system full-scale voltage less than the reference

voltage may also be accounted for a by a system gain calibration.

MAX SYSTEM FULL SCALE

2.5% FROM VREF

ANALOG

INPUT

RANGE

VREF – 1LSB

AGND

SYS FULL S.

ANALOG

INPUT

RANGE

VREF – 1LSB

SYS FULL S.

AGND

SYSTEM GAIN

CALIBRATION

MAX SYSTEM FULL SCALE

2.5% FROM VREF

Figure 29. System Gain Calibration

Finally in Figure 30 both the system offset and gain are ac-

counted for by the system offset followed by a system gain cali-

bration. First the analog input range is shifted upwards by the

positive system offset and then the analog input range is ad-

justed at the top end to account for the system full scale.

ANALOG

INPUT

RANGE

SYS F.S.

SYS OFFSET

VREF + SYS OFFSET

ANALOG

INPUT

RANGE

VREF – 1LSB

SYS F. S.

AGND

SYSTEM OFFSET

CALIBRATION

FOLLOWED BY

SYSTEM GAIN

CALIBRATION

MAX SYSTEM FULL SCALE

2.5% FROM VREF

SYS OFFSET

MAX SYSTEM OFFSET

5% OF VREF

MAX SYSTEM OFFSET

5% OF VREF

AGND

VREF – 1LSB

MAX SYSTEM FULL SCALE

2.5% FROM VREF

Figure 30. System (Gain + Offset) Calibration

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