AD7853_15 datasheet(22/34 Pages) AD

22 / 34 page

REV. B

–22–

AD7853/AD7853L

System Gain and Offset Interaction

The inherent architecture of the AD7853/AD7853L leads to an

interaction between the system offset and gain errors when a

system calibration is performed. Therefore it is recommended to

perform the cycle of a system offset calibration followed by a

system gain calibration twice. Separate system offset and system

gain calibrations reduce the offset and gain errors to at least the

12-bit level. By performing a system offset calibration first and a

system gain calibration second, priority is given to reducing the

gain error to zero before reducing the offset error to zero. If the

system errors are small, a system offset calibration would be

performed, followed by a system gain calibration. If the systems

errors are large (close to the specified limits of the calibration

range), this cycle would be repeated twice to ensure that the

offset and gain errors were reduced to at least the 12-bit level.

The advantage of doing separate system offset and system gain

calibrations is that the user has more control over when the

analog inputs need to be at the required levels, and the

CONVST

signal does not have to be used.

Alternatively, a system (gain + offset) calibration can be per-

formed. It is recommended to perform three system (gain +

offset) calibrations to reduce the offset and gain errors to the

12-bit level. For the system (gain + offset) calibration priority is

given to reducing the offset error to zero before reducing the

gain error to zero. Thus if the system errors are small then two

system (gain + offset) calibrations will be sufficient. If the sys-

tem errors are large (close to the specified limits of the calibra-

tion range), three system (gain + offset) calibrations may be

required to reduced the offset and gain errors to at least the

12-bit level. There will never be any need to perform more than

three system (offset + gain) calibrations.

In Bipolar Mode the midscale error is adjusted for an offset

calibration and the positive full-scale error is adjusted for the

gain calibration; in Unipolar Mode the zero-scale error is ad-

justed for an offset calibration and the positive full-scale error is

adjusted for a gain calibration.

System Calibration Timing

The calibration timing diagram in Figure 31 is for a full system

calibration where the falling edge of

CAL initiates an internal

reset before starting a calibration (note that if the part is in power-

down mode the

CAL pulsewidth must take account of the power-up

time). If a full system calibration is to be performed in software,

it is easier to perform separate gain and offset calibrations so

that the CONVST bit in the control register does not have to be

programmed in the middle of the system calibration sequence.

The rising edge of

CAL starts calibration of the internal DAC

and causes the BUSY line to go high. If the control register is

set for a full system calibration, the

CONVST must be used

also. The full-scale system voltage should be applied to the

analog input pins from the start of calibration. The BUSY line

will go low once the DAC and system gain calibration are

complete. Next the system offset voltage is applied to the AIN

pin for a minimum setup time (tSETUP) of 100 ns before the

rising edge of the

CONVST and remain until the BUSY signal

goes low. The rising edge of the

CONVST starts the system

offset calibration section of the full system calibration and also

causes the BUSY signal to go high. The BUSY signal will go

low after a time tCAL2 when the calibration sequence is complete.

The timing for a system (gain + offset) calibration is very similar

to that of Figure 31, the only difference being that the time

tCAL1 will be replaced by a shorter time of the order of tCAL2 as

the internal DAC will not be calibrated. The BUSY signal will

signify when the gain calibration is finished and when the part is

ready for the offset calibration.

t1 = 100ns MIN, t14 = 50/90ns MIN 5V/3V,

t15 = 2.5 tCLKIN MAX, tCAL1 = 111114 tCLKIN MAX,

tCAL2 = 13899 tCLKIN

(I/P)

BUSY (O/P)

(I/P)

AIN (I/P)

t15

tCAL1

tCAL2

t16

tSETUP

VSYSTEM FULL SCALE

VOFFSET

Figure 31. Timing Diagram for Full System Calibration

The timing diagram for a system offset or system gain calibra-

tion is shown in Figure 32. Here again the

CAL is pulsed and

the rising edge of the

CAL initiates the calibration sequence (or

the calibration can be initiated in software by writing to the

control register). The rising edge of the

CAL causes the BUSY

line to go high and it will stay high until the calibration sequence is

finished. The analog input should be set at the correct level for a

minimum setup time (tSETUP) of 100 ns before the rising edge of

CAL and stay at the correct level until the BUSY signal goes

low.

(I/P)

BUSY (O/P)

AIN (I/P)

SETUP

CAL2

VSYSTEM FULL SCALE OR VSYSTEM OFFSET

Figure 32. Timing Diagram for System Gain or System

Offset Calibration

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