AD7853_15 datasheet(31/34 Pages) AD

31 / 34 page

REV. B

–31–

AD7853/AD7853L

68HC11/L11/16

SCK

CONVST

CLKIN

SCLK

DOUT

BUSY

SM1

SM2

POLARITY

OPTIONAL

4MHz/1.8MHz

SYNC

MISO

DIN AT DGND FOR

NO WRITING TO PART

MASTER

SLAVE

DIN

DVDD

OPTIONAL

IRQ

MOSI

DGND FOR HC11, SPI

DVDD FOR HC16, QSPI

DVDD

SPI

HC16, QSPI

AD7853/AD7853L

Figure 46. 68HC11 and 68HC16 Interface

AD7853/AD7853L to ADSP-21xx Interface

Figure 47 shows the AD7853/AD7853L interface to the ADSP-

21xx. The ADSP-21xx is the slave and the AD7853/AD7853L

is the master. The AD7853/AD7853L is in Interface Mode 5.

For the ADSP-21xx, the bits in the serial port control register

should be set up as TFSR = RFSR = 1 (need a frame sync for

every transfer), SLEN = 15 (16-bit word length), TFSW =

RFSW = 1 (alternate framing mode for transmit and receive

operations), INVRFS = INVTFS = 1 (active low RFS and

TFS), IRFS = ITFS = 0 (External RFS and TFS), and ISCLK

= 0 (external serial clock). The CLKIN and

CONVST signals

could be supplied from the ADSP-21xx or from an external

source. The AD7853/AD7853L supplies the SCLK and the

SYNC signals to the ADSP-21xx and the reading and writing

takes place during conversion. The BUSY signal only indicates

when the conversion is finished and may not be required. The

data access and hold times of the ADSP-21xx and the AD7853/

AD7853L allows for a CLKIN of 4 MHz/1.8 MHz at both 5 V

and 3 V supplies.

ADSP-21xx

SCK

AD7853/AD7853L

CONVST

CLKIN

SCLK

DOUT

BUSY

SM1

SM2

POLARITY

OPTIONAL

4MHz/1.8MHz

SYNC

RFS

DIN AT DGND FOR

NO WRITING TO PART

SLAVE

MASTER

OPTIONAL

DIN

DVDD

OPTIONAL

IRQ

TFS

Figure 47. ADSP-21xx Interface

AD7853/AD7853L to DSP56000/1/2/L002 Interface

Figure 48 shows the AD7853/AD7853L to DSP56000/1/2/L002

interface. Here the DSP5600x is the master and the AD7853/

AD7853L is the slave. The AD7853/AD7853L is in Interface

Mode 3. The DSP56L002 is used when the AD7853/AD7853L

is being operated at 3 V. The setting of the bits in the registers

of the DSP5600x would be for synchronous operation (SYN =

1), internal frame sync (SCD2 = 1), Internal clock (SCKD =

1), 16-bit word length (WL1 = 1, WL0 = 0), frames sync only

active at beginning of the transfer (FSL1 = 0, FSL0 = 1). A

gated clock can be used (GCK = 1) or if the SCLK is to be tied

to the CLKIN of the AD7853/AD7853L, then there must be a

continuous clock (GCK = 0). Again the data access and hold

times of the DSP5600x and the AD7853/AD7853L should

allow for an SCLK of 4 MHz/1.8 MHz.

DSP

56000/1/2/L002

SRD

SCK

AD7853/AD7853L

CONVST

CLKIN

SCLK

DOUT

BUSY

SM1

SM2

POLARITY

OPTIONAL

4MHz/1.8MHz

SYNC

SC2

DIN AT DGND FOR

NO WRITING TO PART

MASTER

SLAVE

OPTIONAL

DIN

DVDD

OPTIONAL

IRQ

STD

Figure 48. DSP56000/1/2 Interface

AD7853/AD7853L to TMS320C20/25/5x/LC5x Interface

Figure 49 shows the AD7853/AD7853L to the TMS320Cxx

interface. The TMS320LC5x is used when the AD7853/AD7853L

is being operated at 3 V. The AD7853/AD7853L is the master

and operates in Interface Mode 5. For the TMS320Cxx the

CLKX, CLKR, FSX, and FSR pins should all be configured as

inputs. The CLKX and the CLKR should be connected to-

gether as should the FSX and FSR. Since the AD7853/AD7853L

is the master and the reading and writing occurs during the

conversion, the BUSY only indicates when the conversion is

finished and thus may not be required. Again the data access

and hold times of the TMS320Cxx and the AD7853/AD7853L

allows for a CLKIN of 4 MHz/1.8 MHz.

TMS320C20/

25/5x/LC5x

CLKR

AD7853/AD7853L

CONVST

CLKIN

SCLK

DOUT

BUSY

SM1

SM2

POLARITY

OPTIONAL

4MHz/1.8MHz

SYNC

FSR

DIN AT DGND FOR

NO WRITING TO PART

SLAVE

MASTER

OPTIONAL

DIN

DVDD

OPTIONAL

INT0

FSX

CLKX

Figure 49. TMS320C20/25/5x Interface

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