REV. B

–24–

AD7853/AD7853L

DETAILED TIMING SECTION

Mode 1 (2-Wire 8051 Interface)

The read and writing takes place on the DIN line and the con-

version is initiated by pulsing the

CONVST pin (note that in

every write cycle the 2/

3 Mode bit must be set to 1). The con-

version may be started by setting the

CONVST bit in the con-

trol register to 1 instead of using the

CONVST line.

Below in Figure 33 and in Figure 34 are the timing diagrams for

Interface Mode 1 in Table X where we are in the 2-wire inter-

face mode. Here the DIN pin is used for both input and output

as shown. The

SYNC input is level triggered active low and can

be pulsed (Figure 33) or can be constantly low (Figure 34).

In Figure 33 the part samples the input data on the rising edge

of SCLK. After the 16th rising edge of SCLK the DIN is con-

figured as an output. When the

SYNC is taken high the DIN is

three-stated. Taking

SYNC low disables the three-state on the

DIN pin and the first SCLK falling edge clocks out the first data

bit. Once the 16 clocks have been provided the DIN pin will

continuous SCLK shown by the dotted waveform in Figure 33

can be used provided that the

SYNC is low for only 16 clock

pulses in each of the read and write cycles. The POLARITY pin

may be used to change the SCLK edge which the data is sampled

on and clocked out on.

In Figure 34 the

SYNC line is tied low permanently and this

results in a different timing arrangement. With

SYNC tied low

permanently the DIN pin will never be three-stated. The 16th

rising edge of SCLK configures the DIN pin as an input or an

output as shown in the diagram. Here no more than 16 SCLK

pulses must occur for each of the read and write operations.

If reading from and writing to the calibration registers in this

interface mode, all the selected calibration registers must be

read from or written to. The read and write operations cannot

be aborted. When reading from the calibration registers, the

DIN pin will remain as an output for the full duration of all the

calibration register read operations. When writing to the calibra-

tion registers, the DIN pin will remain as an input for the full

duration of all the calibration register write operations.

SCLK (I/P)

SYNC (I/P)

t

3

t

8

DIN (I/O)

DB15

DB0

DB0

t

3

t

11

t

6

POLARITY PIN

LOGIC HIGH

116

16

1

t

5A

t

12

DIN BECOMES AN INPUT

DB15

THREE-STATE

DATA READ

DATA WRITE

t

7

t

6

t

14

t

11

DIN BECOMES AN OUTPUT

t

t

Figure 33. Timing Diagram for Read/Write Operation with DIN as an Input/Output (i.e., Interface Mode 1, SM1 = SM2 = 0)

SCLK (I/P)

t

8

DIN (I/O)

DB15

DB0

DB0

t

6

116

16

1

DIN BECOMES AN INPUT

DB15

DATA READ

DATA WRITE

t

7

t

6

t

14

t

t

6

t

13

POLARITY PIN

LOGIC HIGH

Figure 34. Timing Diagram for Read/Write Operation with DIN as an Input/Output and SYNC Input Tied Low

(i.e., Interface Mode 1, SM1 = SM2 = 0)