AN2352

Configuration of the CAN bit timing

9/20

node recognizes if the error is local or global by simply detecting that there is an echo after

its error flag. This is possible only if the node can properly sample the first bit after

transmitting the error flag.

The error flag from an error active node is composed of 6 dominant bits; in the worst case

condition of a bit stuffing error, up to 6 other dominant bits could be received before the error

flag. This means that the first bit after the error flag is the 13th bit after the last

synchronization: This bit, as already stated, must be correctly sampled.

resynchronization edges can be expressed as:

Also in this case, assuming the two CAN nodes have opposite system clock generator

tolerance (considering the specified tolerance "df" valid for both nodes in the network) for

their respective system clocks, the accumulated phase error at the resynchronization instant

becomes:

For a correct sampling, the accumulated phase error must not lead the resynchronization

edge outside the interval Phase_Seg1 + Phase_Seg2. This condition can be expressed as:

Once again, this expression can be translated into a condition for the CAN system clock

tolerance df:

In conclusion, both conditions on the CAN system clock tolerance must be satisfied.

In case the CAN node generates its system clock through a PLL, the maximum allowed

clock tolerance must also be a function of the PLL jitter: This results in a more severe quality

requirement for the oscillator (crystal or resonator).

The phase error introduced by the PLL jitter is linked to the number of clock periods: In

particular, the jitter increases with the clock period number until a saturation maximum value

is attained, which results in the long term jitter (refer to datasheet for more details about the

PLL electrical characteristics).

Considering the PLL effect, the two expressions producing the phase error in the two

conditions above are modified as follows:

where

δ

formulas, the value of

δ

the jitter corresponding to a 10-bit time period must be considered, while for the second, the

jitter corresponding to a 13-bit time period must be considered. The number of clock periods

tS

13

tBT tPB2

–

⋅

=

∆tS

2df

⋅

()

13

tBT tPB2

–

⋅

()

⋅

=

tPB1

2df

⋅

()

<

13

tBT tSeg2

–

⋅

()

⋅

tPB2

<

df

min tPB1 tPB2

,

()

213

tBT tPB2

–

⋅

()

⋅

()

----------------------------------------------------------------

<

∆tJ

2df

10

tBT δPLL

–

⋅⋅

()

⋅

=

∆tS

2df13

tBT tPB2

–

⋅

()

⋅δPLL

+

[]

⋅

=