AN2352

Configuration of the CAN bit timing

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Figure 2.

Propagation time segment

In this example, both nodes A and B are transmitters performing an arbitration for the CAN

bus. Node A has sent its start of frame bit less than one bit time earlier than node B,

therefore node B has synchronized itself to the received edge from recessive to dominant.

Since node B has received this edge delay (A_to_B) after it has been transmitted, B’s bit

timing segments are shifted in relation to A. Node B sends an identifier with a higher priority

and therefore will win the arbitration at a specific identifier bit when it transmits a dominant

bit while node A transmits a recessive bit. The dominant bit transmitted by node B arrives at

node A after the delay (B_to_A).

Due to oscillator tolerances, the actual position of node A’s sample point can be anywhere

inside the nominal range of node A’s phase buffer segments, so the bit transmitted by node

B must arrive at node A before the start of Phase_Seg1. This condition defines the length of

Prop_Seg.

If the edge from recessive to dominant transmitted by node B would arrive at node A after

the start of Phase_Seg1, it is possible that node A samples a recessive bit instead of a

dominant bit, resulting in a bit error and the destruction of the current frame by an error flag.

The error occurs only when two nodes with oscillators at opposite ends of the tolerance

range and separated by a long bus line arbitrate for the CAN bus; this is an example of a

minor error in the bit timing configuration (Prop_Seg too short) that causes sporadic bus

errors.

1.3

Phase buffer segments and synchronization

The phase buffer segments (Phase_Seg1 and Phase_Seg2) and the synchronization jump

width (SJW) are used to compensate the oscillator tolerance. The phase buffer segments

may be lengthened or shortened by synchronization.

Synchronizations occur on edges from recessive to dominant; their purpose is to control the

distance between edges and sample points.

Edges are detected by sampling the actual bus level in each time quantum and comparing it

with the bus level at the previous sample point. A synchronization is possible only if a

Sync_Seg

Prop_Seg

Phase_Seg1

Phase_Seg2

Node B

Node A

Delay A_to_B

Delay B_to_A

Prop_Seg

>= Delay A_to_B + Delay B_to_A

Prop_Seg

>= 2 • [max(node output delay + bus line delay + node input delay)]

Delay A_to_B >= node output delay(A) + bus line delay(AÆB) + node input delay(B)