AN2352

Configuration of the CAN bit timing

13/20

1.6.1

Example for bit timing at high baud rate

In this example, CPU clock frequency is 40 MHz, the frequency of the CAN module clock is

20 MHz, BRP is 1 and the bit rate is 1 Mbit/s. By default, the ST10F27x divides by 2 the

clock that feeds the CAN cells (mandatory when the CPU clock frequency is higher than

40 MHz). It is possible to disable this function by setting bit 2 of the XMISC register.

100 ns

delay of bus driver

50 ns

delay of receiver circuit

30 ns

delay of bus line (40m)

220 ns

600 ns

100 ns

700 ns

200 ns

100 ns

100 ns

bit time

1000 ns

tolerance for CAN clock

=

tolerance for CAN clock

= 39%

min

min PB1 PB2

(,

)

2

13

bit_time

⋅

PB2

–

()

⋅

-----------------------------------------------------------------------

tSJW

()

210

tBT

⋅⋅

----------------------------------

,

⎝⎠

⎛⎞

min PB1 PB2

(,

)

2

13

bit_time

⋅

PB2

–

()

⋅

-----------------------------------------------------------------------

0.1

µs

213

1

µs0.2µs

–

⋅

()

⋅

------------------------------------------------------------

039%

,

==

tSJW

()

210

tBT

⋅⋅

----------------------------------

0.1

µs

210

1

µs

⋅

()

⋅

---------------------------------------

05%

,

==