TN0897

General description

Doc ID 023176 Rev 2

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Figure 1.

ST SPI signal description

The SPI can be driven by a microcontroller with its SPI peripheral running in following mode:

CPOL = 0 and CPHA = 0.

Figure 2.

SPI signal description

The communication starts at the CSN transition from High to Low. SCK is initially Low.

Data at SDI must be stable at the first SCK transition from Low to High.

Data at SDO is shifted at the first falling edge of SCK.

CSN transition Low to High must occur after the specified number of clock cycles (rising and

falling edges of SCK are counted).

SCK

SDI

SDO

CSN

FSTAT

optional