TN0897

Read and clear status operation

Doc ID 023176 Rev 2

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6

Read and clear status operation

The <Read and Clear Status> operation starts with a Command Byte followed by 1, 2, or 3

data bytes. The number of data bytes is specified in the <SPI-frame-ID>. The content of the

data bytes is ‘don’t care’. The content of the addressed status register is transferred to SDO

within the same frame (‘in-frame response’) and is subsequently cleared.

A <Read and Clear Status> command addressed to the <Configuration> register

(RAM: 3FH) clears all status registers (incl. the <Global Status> register) simultaneously

and reads back the <Configuration> register.

6.1

Read and clear status command format

Figure 11.

Read and clear status command format

A0 to A5: address bits

Command byte

MSB

LSB

Op Code

Address

1

0

A5

A4

A3

A2

A1

A0

Data byte 1

MSB

LSB

0

0000

00

0

1.

Only for 24-bit SPI frame width.

MSB

LSB

0

0000

00

0