TN0897

SPI communication flow

Doc ID 023176 Rev 2

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Figure 4.

Global error flag definition

The open-drain <FSTAT> pin is an optional feature which reflects the status of the <Global

Error Flag> (Bit 7 of the <Global Status> register). Several <FSTAT> pins in a system can be

connected to one microcontroller I/O port in order to indicate an error in the system. The

faulty device can then be identified by reading the <Global Error Flag> bits of all devices.

The <Global Error Flag> is also available on the SDO pin while CSN is low and the clock

signal is stable (high or low). The flag at SDO remains as long as CSN is low. This operation

does not set the <communication error> bit in the <Global Status Register>. The refresh-

procedure of the GEF at SDO is device specific.

A status change during an SPI communication can cause an inconsistency in the <Global

Status> register and other Status Registers. For devices intended for safety critical

applications, precautions must be taken to avoid such inconsistencies.

2.4

Configuration register (optional)

The <Configuration> register is optional. When available, it is always accessible at RAM

address 3FH.

Watchdog Trigger Bit:

Configuration Register

(RAM: 3FH; Bit 0)

Watchdog

Watchdog Trigger

Signal

Clock

Monitor

SCK

CSN

Communication

Error

Global Status Register

Fail

Safe

GEF

FSTAT

optional

SDO / Err

Fail Safe Events

(device specific)

Watchdog Failure

OR

SDI

SDI failure

detection

Status Registers

(device specific)

OR

GAPGCFT00721