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AN3112 数据表(PDF) 6 Page - STMicroelectronics

部件名 AN3112
功能描述  Solution for designing a fixed off-time controlled PFC pre-regulator
PDF  36 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

AN3112 数据表(HTML) 6 Page - STMicroelectronics

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Implementing the line-modulated fixed-off-time
AN3112
6/36
Doc ID 16820 Rev 3
3
Implementing the line-modulated fixed-off-time
The circuit that implements LM-FOT control with the L6564 PFC controller is shown in
Figure 6. During the on-time of the MOSFET the gate voltage V
GD = 15 V is high, diode D is
forward biased and the voltage at the ZCD pin is internally clamped at VZCDclamp (5.7 V
typ.). During the MOSFET off-time VGD is low, diode D is reverse-biased and the voltage at
the pin decays with an exponential law until it reaches the triggering threshold (VZCDtrigger ~
0.7 V typ.) which causes the switch to turn on. The time needed for the ZCD voltage to go
from VZCDclamp (clamping level) to VZCDtrigger (trigger level) defines the duration of the off-
time, or TOFF.
Figure 6.
Circuit implementing FOT control with the L6564
The circuit in
Figure 6. makes T
OFF a function of the RMS line voltage thanks to the peak
holding effect of T1 (which acts as a buffer) along with R and C whose time constant is
significantly longer than a line half-cycle. With the addition of R0 and T1, as long as the
voltage on the ZCD pin during TOFF is above Vmult+VBE, C is discharged through R and R0,
following the law:
Equation 1
As V’ZCD(t) falls below Vmult+VBE, T1 is cut off and C is discharged through R only, so that its
evolution from that point on is described as:
Equation 2
V'ZCD(t) decreases from VZCDclamp = 5.7 V to Vmult+VBE in the following time period t':
()
()
()
BE
mult
0
C
RR
)
R
R
(
t
BE
mult
0
ZCDclamp
ZCD
V
V
R
R
R
e
V
V
R
R
R
V
)
t
(
V
0
0
+
+
+
+
+
=
+
()
C
R
t
BE
mult
0
ZCD
e
V
V
R
R
R
)
t
(
V
+
+
=
′′



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