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AN3112 数据表(PDF) 8 Page - STMicroelectronics |
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AN3112 数据表(HTML) 8 Page - STMicroelectronics |
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8 / 36 page ![]() Implementing the line-modulated fixed-off-time AN3112 8/36 Doc ID 16820 Rev 3 It is easy to see that TOFF is now a function of the instantaneous line voltage. We refer to this technique as line-modulated fixed-off-time (LM-FOT) [ 5]. This modification, although simple, introduces profound changes in the timing relationships, with a positive influence on the energetic relationships. From the control point of view, modulating TOFF is a feed-forward term that modifies the gain but does not change its characteristics. Consequently, all of the properties of the standard FOT control are maintained. Due to the highly non-linear nature of the TOFF modulation introduced by T1 and R0, its effects are discussed only qualitatively and the quantitative aspects are provided graphically for a specific case in [ 5]. As a practical rule, it is convenient to first select a capacitor and then to calculate the resistor needed to achieve the desired TOFF (see Section 4.3.7 on page 19). As the gate voltage VGD rises, the Rs resistor charges the C timing capacitor as quickly as possible up to VZCDclamp, without exceeding the clamp rating (IZCDx =10 mA). Then it must fulfill the following inequalities: Equation 6 where VGD (assume VGD = 10 V) is the voltage delivered by the gate driver, VGDx = 15 V its maximum value, and VF the forward drop on D. When working at high line/light load the on-time of the power switch becomes very short and the Rs resistor alone is no longer able to charge C up to VZCDclamp. The speed-up capacitor Cs is then used in parallel to Rs. This capacitor causes an almost instantaneous charge of C up to a certain level, after that, Rs completes the charge up to VZCDclamp. It is important that the steep edge caused by Cs does not reach the clamp level, otherwise the internal clamp of the L6564 undergoes uncontrolled current spikes (limited only by the dynamic resistance of the 1N4148 and the ESR of Cs) that could overstress the IC. Cs must then be: Equation 7 ZCDclamp F ZCDclamp GD ZCDclamp ZCDx F ZCDclamp GDx V V V V R Rs R V I V V V − − ⋅ < < + − − F ZCDclamp GDx ZCDclamp V V V V C Cs − − < |
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