AN2156

4 - Boot management

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4

Boot management

4.1

SystemMemory / User Boot mode pins M0, M1

The recommended circuitry around the mode pins M0 and M1 depends upon the end of line

programming strategy for virgin devices. The device always operates (i.e. executes the

application) in user boot mode and it is also possible to program the device via the JTAG debug

port in this mode. Field updates, where the application is already running and updating itself,

also use this mode. Depending solely on the application, any interface may be used for field

updates such as CAN or UART.

The support of SystemMemory boot mode is necessary only when virgin devices or

applications which are not able to update themselves, are programmed via CAN or UART.

Please note that circuitry is needed that supports both user and SystemMemory boot modes.

ST prefers programming via the JTAG port, since it provides the fastest possible method, no

interface resources are necessary, the handling is easier and a lot of professional end-of-line

programming solutions already exist from well known companies such as PLS and BP

Microsystems.

4.1.1

End of line programming via JTAG

If you know already that you will program the devices only via the JTAG debug port, simply

connect both mode pins M0 and M1 directly or via pull-down resistors to GND.

Figure 6.

M0 and M1 pin connections

4.1.2

End of line programming via UART or CAN

If you are not yet sure which end of line programming method to use or you know that you will

use the SystemMemory boot mode method, you need dynamic handling of the mode pins.

The voltage levels on the mode pins are latched with a rising edge on the reset pin. When both

M0 and M1 are low at this time then user boot mode is entered. When M0 is low and M1 high at

this time then SystemMemory boot mode is entered and the testflash sector is aliased at

address 0 instead of the normal sector 0.

As long as M1 stays high the clock is stretched and no code is executed. So in order to run the

bootstraploader code of the testflash sector a falling edge on M1 is needed some time after the

rising edge on reset. This time is not critical but must exceed 500ns. The following figure shows

the timing.

M0

M1