AN2156

5 - Debug management

13/24

The JTAG input signals have weak internal pull-up and pull-down resistors, but these are not

always active:

●

When debug protection is activated (JTAG permanently held in reset internally)

●

At power up and down there may be a short duration where the power on reset is already

released internally, but where the resistors are not yet active.

To avoid any floating input pins even for a very short period it is highly recommended to always

provide additional external pull-up and pull-down resistors. This recommendation is valid

whether the JTAG port is used or not.

The following table shows the recommended values and types:

Table 4.

Recommended JTAG debug port components

To connect the target with a debugger some additional signals are needed, mainly the System

Reset nRSTIN, so that the debugger can also reset the whole MCU, not only the JTAG part.

nRSTIN should be an open collector so that the different reset sources (power-on reset

circuitry, ext. watchdog if available and the JTAG equipment/Debugger) can be connected

together. The Debugger itself will also monitor the level on nRSTIN, so that it recognizes when

a reset is forced by some other circuitry.

Finally the target supply voltage must be provided so that the Debugger may adapt voltage

levels appropriately.

TDO

JTDO

Test data out (to JTAG

equipment)

TDO is the return path of the data input

signal TDI.

nSRST

nRSTIN

System reset

(bidirectional)

nSRST is an active LOW open-collector

signal that can be driven by the JTAG

equipment to reset the target board. Some

JTAG equipment senses this line to

determine when a board has been reset by

the user.

When the signal is driven LOW by the reset

controller on the core module, the

motherboard resets the whole system by

driving nSYSRST low.

DBGRQ

GND

(not used)

Debug request (from

JTAG equipment)

DBGRQ is a request for the processor core

to enter debug state.

DBGACK

GND

(not used)

Debug acknowledge (to

JTAG equipment)

DBGACK indicates to the debugger that the

processor core has entered debug mode.

Signal name

Recommended external

Resistor type

Recommended value

JTCK

Pull-down between pin and VSS/

GND

10k

Ω

JTDI

Pull-up between pin and VDD/

VCC

10k

Ω

JTDO

Output, no resistor needed

N.A.

JTMS

Pull-up between pin and VDD/

VCC

10k

Ω

JTRST

Pull-down (*) between pin and

VSS/GND

10k

Ω

Std name

STR73x name

Direction/Description

Function