1 - Power management

AN2156

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1

Power management

1.1

Power supply pins VDD/VSS

All current STR73x devices are supplied with a nominal voltage of 5V. The power supply pins

are organized in VDD/VSS pairs around the chip and exceptionally all pins need to be properly

connected to the power supplies, VDD to 5V, VSS to GND. These connections including pads,

tracks and vias should have an impedance as low as possible. This is typically achieved with

thick track widths and preferably dedicated power supply planes in multi layer PCBs.

In addition, each VDD/VSS pair should be decoupled with ceramic capacitors which need to be

placed as close as possible to the appropriate pins or below the pins on the contrary side of the

PCB. Typical values are 10nF to 100nF, but exact values depend on the application needs. The

following figure shows the typical layout on such a VDD/VSS pair.

Figure 1.

Typical layout for VDD/VSS pair

1.2

X7R ceramic capacitor of 47nF to 100nF can be used for this.

When full accuracy is needed, and depending on the noise rejection of the voltage regulator

used to supply the STR73x device, a low pass filter may be considered. As the pin is also used

as the ADC supply, the use of a serial resistor must be avoided to reduce the risk of offset error

generation. An EMI component from Murata is proposed instead.

Via to VSS

Via to VDD

Cap.

STR73x