AN2156

1 - Power management

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Figure 2.

1.3

Decoupling of the internal voltage regulator V18

All existing STR73x derivates are supplied with a single external voltage of 5V. The additional

voltages needed are generated by internal charge pump circuits for the flash programming/

erasing and an internal linear voltage regulator which provides the 1.8V for the internal logic.

The output of the internal voltage regulator is connected to one or two pins V18, where an

external capacitance needs to be connected for decoupling/stabilization between the V18 pin

and VSS/GND. There are two important notes:

1.

V18 is probably the most critical pin regarding EMC emissions. Therefore the external

capacitor(s) must be placed as close as possible (few mm) to the V18/VSS pair(s) or

below on the other side of the PCB. If this is done, a very good EMC performance can be

achieved.

2.

Depending on the device, different capacitances are needed. The values mainly depend

on the type of the internal voltage regulator used. Please refer to the tables below which

cover the devices available or planned at the time of writing. In case of future devices

which are not covered by this application note please refer to the datasheet or contact your

support engineer.

The figure below shows the two affected pins (V18 and VBias) of the TQFP144 package as well

as the TQFP100 package. In order to support all devices with a single PCB design, it is

necessary to provide on both pins footprints for 10µF tantalum and 47-100nF ceramic

capacitors. The footprint for the ceramic capacitor on pin 64 should be reusable to be soldered

with a resistor instead for the biasing functionality. This may be achieved with 0805 or 0603

SMD footprints. Please refer to the tables below for the different component values and

assembly options depending upon the device derivate.

C1 = 47 to 100nF X7R ceramic capacitor

U1 = Murata NFM18PC105R0J3 – 1uF

C1

U1

+5V