AN2647

Interfacing with asynchronous memory

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Read bus cycle timing configuration

Figure 3. shows a typical Read Bus Cycle. All bus timings are referenced to the internal

BCLK clock signal. BCLK clock is only available on an external pin for various usage on the

144 pin BGA package.

Figure 3.

Read bus cycle, 16-bit multiplexed bus

EMI_ALE signal configuration

The EMI_ALE signal is used to latch the address A0-15 by the external address latch, or as

a direct input to memory device that have an ALE pin. The EMI_ALE by default is one BCLK

period in length with active high polarity. It can be programmed to be 2 BCLK period in

asynchronous mode and the polarity can be active low. The ALE length and polarity are

defined in the SCU_SCR0 register.

Address A0-A15 are valid at the leading edge of EMI_ALE and are driven for another half

BCLK period after the trailing edge. The AD bus is tri-stated after the address phase is over.

A16-23 are not multiplexed and remain stable until the end of the bus cycle.

EMI_RD signal configuration

The EMI_RDn timing is controlled by the WSTRD value in the EMI_RCRx register (Read

Wait State Control) and the WSTOEN value in the EMI_OECRx register (Output Enable

Control).

●

WSTOEN: Output Enable. WSTOEN specifies the delay between the assertion of the

chip select and the time EMI_RDn signal goes low. The delay is defined in terms of

The minimum WSTOEN value is 2 in a multiplexed bus (for ALE with one BCLK period

of the bus cycle.

●

WSTRD: Read wait state. WSTRD specifies the pulse width, or the rising edge of

WSTOEN+1).