Interfacing with asynchronous memory

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Interfacing with asynchronous memory

1.1

Multiplexed or non-multiplexed EMI bus selection

The multiplexed EMI bus is selected if you have a 16-bit system bus or using 16-bit memory

device. The multiplexed bus requires a 16-bit address latch, as most memory devices do not

accept multiplexed address/data input.

The 8-bit non-multiplexed bus is suitable for 8-bit memory or I/O devices. In this

configuration, the EMI memory banks are limited to 64 KB each, as there are only 16

address lines available.

In general the non-multiplexed bus has a shorter bus cycle that can be completed in one bus

multiplexed bus has a 16 bit data bus, and can provide high data transfer rate for memory

device like PSRAM that supports burst mode. The DMA Controller can be programmed to

perform burst data transfer between the internal SRAM and the EMI bus.

1.1.1

Multiplexed EMI bus configuration

The multiplexed bus has different bus signals and port assignments than the non-

multiplexed bus. As shown in Table 1, Ports 8 and 9 provide the multiplexed 16 bit address

and data bus (AD0-AD15), the optional higher address A16-A23 are assigned to Port 7.

Figure 1. & Figure 2. show a typical EMI multiplexed bus connecting to two 16-bit memory

devices: a 4 MB ISSI SRAM and a 4 MB SPANSION Flash memory. The SN74LVC16373A

on Port 7 are address lines, the remaining four pins are for other I/O functions.

Table 1.

Multiplexed bus signals

Signal name

Pin / Port assignment

Signal description

AD0-AD7

Port 8

Multiplexed address/data bus AD0-AD7

AD8-AD15

Port 9

Multiplexed address/data bus AD8-AD15

A16-A23

Port 7

Address A16-A23, pin configurable

ALE

EMI_ALE

Address Latch signal. Polarity and width is programmable

Read

EMI_RDn

Read signal

Write Low

(Low Byte Select)

EMI_BWRn

(EMI_WRLn or EMI_LBn)

Low Byte (D0-D7) Write signal or

Low Byte Select signal.

Write High

(High Byte Select)

EMI_WRHn

(EMI_UBn)

High Byte (D8-D15) Write signal or

High Byte Select signal

Write Enable

EMI_WEn

Write Enable signal, use together with the UB/LB byte

select signals in synchronous mode.

CS0-CS3

Port 0(P0.4-P0.7) or

Port 5 (P5.4-P5.7) or

Port 7 (P7.4-P7.7)

One chip select for each of the 4 Memory Banks.Can be

assigned to any of the 3 port.