AN2647

Interfacing with asynchronous memory

13/34

Write bus cycle timing configuration

Figure 8. shows a typical Write Bus Cycle. The write bus cycle timing differs from the read

bus cycle in two ways:

Figure 8.

Write bus cycle, non-multiplexed bus

– The write signal (EMI_BWRn) aligns with the falling edge of the BCLK

EMI_BWR signal configuration

The EMI_BWRn signal timing is controlled by the WSTWR value in the EMI_WCRxn

register (Write Wait State Control) and the WSTWEN value in the EMI_WECRx (Write

Enable Control) register.

●

WSTWEN: Write Enable. WSTWEN specifies the delay period between the assertion

of the CSx chip select and the falling edge of EMI_BWRn. The delay is defined in terms

of BCLK clock periods and is (WSTWEN + 1/2) for asynchronous write cycles. The

minimum WSTWEN value can be 0 in a non-Multiplexed bus.

●

WSTWR: Write wait state. WSTWR specifies the pulse width of EMI_BWRn. The pulse

width is defined in terms of BLCK period and is equal to (WSTWR-WSTWEN+1) for

asynchronous write cycles.

The choice of the WSTWEN and WSTWR values depend on the address setup time, data

time. The WSTWR or pulse width is set accordingly to meet the memory's data setup time

requirement.

The WSTWEN and WSTWR are set to one in Figure 8., providing address setup time of

Half word and word access in 8-bit non-multiplexed mode

In the 8-bit non-multiplexed mode, the CPU is able to read or write 16-bit or 32-bit data using

the assembly instruction of STRH, LDRH or STR, LDR. For 16-bit access, the EMI

generates two consecutive 8-bit bus cycles; while 32-bit access results in 4 consecutive 8-