AN2647

Interfacing with synchronous memory

31/34

EMI burst write bus cycle

In synchronous mode the write signal WEn is sampled at the same time the address is

latched. This requires the write assertion delay WSTWEN to be "0" so WEn will stay low at

the beginning of the bus cycle. STR91xFA always writes to PSRAM in 16-bit mode and the

two byte-select signals UB/LB are low for the entire write cycle.

The latency counter in the BCR register defines when the write data is sampled by PSRAM,

and this time has to match the EMI write timing so the first write data is latched at the right

clock edge. In this example the write wait state WSTWR is set to 5 and the latency counter

is set to 4. Refer to the MT45W4M data sheet for the timing details.

Figure 16.

EMI write bus cycle in burst mode

Note:

The EMI_BAA signal is not needed for the PSRAM interface.