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Interfacing with synchronous memory

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2.2.1

PSRAM bus operating modes

The MT45W4M supports multiple configurations in Asynchronous mode, Synchronous burst

mode, and Page mode. Page mode requires a non-multiplexed bus connection and is not

compatible with the EMI bus.

In this application note, only the PSRAM configurations that are compatible to the EMI bus

are discussed. The EMI bus supports both the asynchronous and synchronous mode; The

mode can be changed by software on the fly to match the PSRAM bus cycle. Typically,

Synchronous burst mode is recommended for high speed data transfer, while asynchronous

mode is used by the EMI bus to:

– Read or write a single halfword to the PSRAM

– Configure the PSRAM registers

Asynchronous mode

After power up the MT45W4M is default to asynchronous mode. There are variations of

asynchronous mode, the one that the EMI bus can support is the "Asynchronous access

Using ADV". The read bus timing is shown in Figure 12. Please note the address inputs are

latched by the rising edge of ADV# and become "don't care" after the latching. The PSRAM

WAIT# output signal is not used in asynchronous mode and is ignored by the EMI.

Figure 12.

PSRAM asynchronous read using ADV (EMI_ALE)