AN3100

DDR overview

Doc ID 16606 Rev 2

9/24

For example, the situation for the cut 128 Mb x 8 in eight and four bank mode is shown

below:

●

128 Mb x 8 (eight bank mode, all 3 bank address bits are used)

–

User_address [0] = datapath;

–

User_address [10:1] = column address;

–

User_address [13:11] = bank address;

–

User_address [27:12] = row address;

–

User_address [28] = chip select;

●

128 Mb x 8 (four bank mode, only 2 bits are used for the bank address)

–

User_address [0] = datapath;

–

User_address [10:1] = column address;

–

User_address [12:11] = bank address;

–

User_address [26:13] = row address;

–

User_address [27] = chip select;

SPEAr3xx supports DDR mobile and DDR2 devices. The memory controller needs to be

configured once at system startup depending on the memory type, size, and vendor and on

the frequency you want to work with.

2.3

DDR mobile overview

In addition to DDR2, SPEAr3xx also supports DDR mobile for low power consumption

applications, such as battery powered devices. Of course, the clock frequency and hence

the bandwidth of DDR mobile is reduced comared to DDR2.

DDR mobile has the following special features:

●

Temperature-compensated self refresh (TCSR)

This is an on-chip temperature sensor that controls the refresh interval based on the

device temperature.

●

Partial-array self refresh (PASR)

For power savings, the PASR feature enables the controllers to select the amount of

memory that will be refreshed during the self refresh.

●

Deep power-down (DPD)

Deep power-down mode effectively cuts the power to the array and decreases leakage

current. Applications that do not require data retention can use the DPD feature while

the system power is maintained. Data is not retained after the device enters DPD

mode.

●

Clock stop mode

Clock stop mode can be used to save power in the application by reducing the number

of transitions in the clock path. Power savings can be achieved by selecting either of

the following methods:

–

Change the clock frequency when the data transfers require a different rate of

speed

–

Hold CKE HIGH, with CK LOW and CK# HIGH for the full duration of clock stop

mode

Both methods are specific to the application and its requirements, and both methods

enable power savings by reducing the number of transitions in the clock path.