AN3100

DDR overview

Doc ID 16606 Rev 2

5/24

2

DDR overview

2.1

DDR2 vs. DDR1

DDR1 and DDR2 memory modules are widely used in desktop PCs. Their full name is DDR

(double data rate) SDRAM (synchronous DRAM), which is a variant of dynamic RAM.

Dynamic RAM differs from static RAM because the former, constituted by both transistors

and capacitors, requires constant refreshing to restore the values in the capacitors while the

latter, constituted only by transistors, does not require refreshing, resulting in much higher

performance. However, SRAMs are much more expensive than DRAMs.

Going back to SDRAM, this type of memory utilizes a synchronous interface: this means

that it waits for a clock pulse to transfer data, and thus it is synchronized with the system bus

and the processor. SDRAM transfers one bit (per data line) of data per clock cycle.

DDR SDRAM technology doubles the bandwidth of SDRAM under optimal conditions. In

fact, SDRAM transfers data on every clock cycle (to be specific, on the rising edge of every

clock cycle), while DDR transfers data on both the rising and the falling edge of a clock

cycle. Therefore, two bits (per data line) are transferred on every clock cycle. In order to do

this, two bits are accessed from the memory array (where data is actually stored) for each

data line on every clock cycle, this process is called the “2-bit prefetch”. In this way, the

interface’s clock speed remains constant, but the data bus effectively doubles in frequency.

The figure below shows a simple DDR1 SDRAM architecture example.

Figure 2.

DDR1 SDRAM architecture

In general, a DRAM (non synchronous) address is presented in two parts: a row and a

column address. The row and the column are multiplexed on the same set of address pins

(DDR_MEM_ADDR [14:0] with reference to SPEAr3xx pins) to reduce package, size and

cost. First, the row address is loaded, or strobed, into the row address latch via the row

address strobe, or RAS, followed by the column address with the column address strobe, or

CAS. The Read data propagate to the output after a specified access time. Write data are

presented at the same time as the column address, because it is the column strobe that

actually triggers the transaction, whether read or write. The SDRAM internal state logic

operates on discrete commands that are presented to it. The signals RAS and CAS

(DDR_MEM_RAS and DDR_MEM_CAS, SPEAr3xx pins) are still present, but they function

as part of other control signals to form commands rather than simple strobes.

Most of the input signals to the state logic shown in Figure 2 combine to form the discrete

commands listed in Table 2.