SPEAr3xx memory controller overview

AN3100

4/24

Doc ID 16606 Rev 2

Note:

RAS_L, RAS_H and RAS_E are specific ports that can be used in customized SPEAr MPUs

to connect masters to the external DDR.

This memory controller supports DDR mobile and DDR2 devices, compliant with JEDEC

standards, up to a clock frequency of 333 MHz (data rate 667 MT/sec). As the memory

controller supports DDR mobile and DDR2 at different frequencies for almost all DDR part

manufacturers, MPMC must be programmed with the right timing parameters required for

the selected DDR memory part, DDR frequency, CAS latency etc.

Table 1.

Memory controller AHB data ports

Memory controller AHB data port

Driving masters

M0

CPU

M1

RAS_L

M2

DMA master 1, RAS_H

M3

DMA master 2, Ethernet GMAC, C3, RAS_E

M4

USB subsystem, C3