AN3100

SPEAr3xx memory controller overview

Doc ID 16606 Rev 2

3/24

1

SPEAr3xx memory controller overview

In the SPEAr3xx embedded MPU, different memory controllers provide interfaces between

the system elements/blocks and external memory.

The MPMC multi-port memory controller is used for interfacing DDR (double data rate)

synchronous dynamic RAM (SDRAM). It is also responsible for reliable read-write

operations to the memory. In a powerful system like SPEAr3xx, there are several system

elements which may need to communicate with external DDR memory at any time to

increase system efficiency. This is possible because the memory provides data at very high

speed and system elements need time to process that data, so this time can be utilized by

other system elements to transfer data to/from the memory. For example, during the time

that the CPU processes some data or instructions, another master interface (CPU or DMA)

can read or write to the memory. This can be handled by the MPMC’s multi-port capablity.

For maximum flexibility the MPMC has one AHB slave port to configure the memory

controller registers and five AHB slave ports for data. Figure 1: SPEAr3xx architecture gives

an overview of the SPEAr3xx, showing the connections between the SDRAM controller AHB

data ports (M0,..,M4) and the various subsystems of the design.

Figure 1.

SPEAr3xx architecture

In order to understand how the various IPs interact with the external memory through the

multi-port memory controller, the table below shows the driving masters present in

SPEAr3xx and the corresponding memory controller AHB slave data port.

SRAM

74.5 KB

L

F

I

H

Cell array

(reconfigurable

array

subsystem)

300 000 gates

ARM926EJS

32 KI/32 KD

coprocessor

cache

TCM-I/D

CPU

ARM subsystem

Int

ctrl

GPIO

Timer

MPMC

DDR1-2

M0

M1

M2

M3

CFG

M4

1

2

2

3

5

6

7-34

1234

3-12

7

5-23

85

Multilayer bus interconnection matrix

UART

SPI

I2C

JPEG

(Codec)

RAM

(8 KB)

IrDA

Low-speed subsystem

C3

System

Ctrl

Flash

serial

GPIO

RTC

Timer

Timer

DMA

(8 chan.)

ROM

32 KB

WDT

Ethernet

MAC

USB2.0

Device

USB2.0

Host

USB2.0

Host

Application

subsystem

Basic subsystem

HS subsystem

A

B

C

D

Common subsystems

SRAM

74.5 KB

RI-O

Configurable cell array subsystem

SPEAr300

ADC

Misc

9-4

10-6

4

M

Q

P

6-67

G

E

2-12(4)

4-12