AN3100

DDR controller delay lines tuning

Doc ID 16606 Rev 2

13/24

5

DDR controller delay lines tuning

There are certain JEDEC timing requirements for DDR signals on the memory part side for

writes and at the controller side for reads. All DRAM and memory controller manufacturers

follow these timing specifications for reliable data read/write. Because of PCB properties (for

example, track lengths, impedance, device Substrate, memory loading, etc), it is necessary

to tune these signals/parameters in order to be in accordance with the specifications and

maximize the specifications margin for the signals at DRAM and memory controller side.

This tuning can be done by delaying/shifting the signals (DQS and data) with respect to

each other and the core clock.

5.1

Reading from DRAM

DDR (dual data rate) memories send a data strobe (DQS) signal coincident with the read

data so that the read data can be reliably captured by the memory controller. The edges of

this strobe are aligned with the data output by the DRAM devices. The paths for the data

and the associated data strobe signals should be routed with the same length between the

capture logic and the DRAM devices, allowing the rising and falling edges of the data strobe

to arrive at the capture logic at the same time the data is in transition. However, the raw data

strobe signal cannot be used as a clock to capture the data, since the data will not be stable

when the data strobe edges are rising and falling. Instead, a delayed version of the data

strobe signal must be used to capture the data. The delay added to the data strobe signals

should be such that the margin to capture the read data is maximized. Because the

frequency of the data strobe signal is matched to the system clock, the delay is a relative

number based on the period of the system clock.

On SPEAr devices, this delay is managed by dll_dqs_delay_1 and dll_dqs_delay_0

parameters (MPMC_Register_39, at offset 0x9C from base address of MPMC) respectively

for upper 8 bits and lower 8 bits of the memory datapath.

5.2

Writing to DRAM

DDR memories require that the DQS data strobe arrives at the DDR within a certain window

around the clock. This value (tdqss) is specified in fractions of a clock cycle. Most DRAM

devices specify this value between +/- 0.25 and 0.2 of a clock cycle. This translates to a

valid window of between 0.5 and 0.4 of a clock cycle.

The DRAM devices expect the data strobe signal to be shifted by the memory controller in

order to allow the DRAM the maximum margin for capturing the data with the data strobe

signal sent to the DRAM devices from the memory controller.

The DLL maintains two delay lines for sending write data and the write data strobe. The first

delay line delays the main clock so that the write data strobe transition reaches the DRAM

as synchronously as possible with the clock edge under typical operating conditions. The

second delay line adjusts the clock that is used to output the write data. This clock should be

adjusted to maximize the setup and hold requirements around the write strobe.

Both the DQS (for write) and Data (DQ) signals from the SPEAr device are controlled by the

programmable parameters dqs_out_shift (MPMC_Register_40, at offset 0xA0 from base

address of MPMC) and wr_dqs_shift (MPMC_Register 41, at offset 0xA4 from base address

of MPMC). These two parameters for writes are valid for both bytes that constitute the