PM0044 datasheet(17/162 Pages) STMICROELECTRONICS

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PM0044

STM8 memory interface

Doc ID 13590 Rev 3

17/162

STM8 memory interface

4.1

Program space

The program space is 16-Mbyte and linear. To distinguish the 1, 2 and 3 byte wide

addressing modes, naming has been defined as shown in Figure 3:

●

"Page" [0xXXXX00 to 0xXXXXFF]: 256-byte wide memory space with the same two

most significant address bytes (XXXX defines the page number).

●

"Section" [0xXX0000 to 0xXXFFFF]: 64-Kbyte wide memory space with the same most

significant address byte (XX defines the section number).

The reset and interrupt vector table are placed at address 0x8000 for the STM8 family.

(Note: the base address may be different for later implementations.) The table has 32 4-byte

entries: RESET, Trap, NMI and up to 29 normal user interrupts. Each entry consists of the

reserved op-code 0x82, followed by a 24-bit value: PCE, PCH, PCL address of the

respective Interrupt Service Routine. The main program and ISRs can be mapped

anywhere in the 16 Mbyte memory space.

CALL/CALLR and RET must be used only in the same section. The effective address for the

CALL/RET is used as an offset to the current PCE register value. For the JP, the effective

address 16 or 17-bit (for indexed addressing) long, is added to the current PCE value. In

order to reach any address in the program space, the JPF jump and CALLF call instructions

are provided with a three byte extended addressing mode while the RETF pops also three

bytes from the stack.

As the memory space is linear, sections can be crossed by two CPU actions: next

instruction byte fetch (PC+1), relative jumps and, in some cases, by JP (for indexed

addressing mode).

Note:

For safe memory usage, a function which crosses sections MUST:

- be called by a CALLF

- include only far instructions for code operation (CALLF & JPF)

All label pointers are located in section 0 (JP [ptr.w] example: ptr.w is located in section 0

and the jump address in current section)

Any illegal op-code read from the program space triggers a MCU reset.

4.2

Data space

The data space is 16-Mbyte and linear. As the stack must be located in section 0 and as

data access outside section 0/1 can be managed only with LDF instructions, frequently used

data should be located in section 0 to get the optimum code efficiency.

All data pointers are located in section 0 only.

Indexed addressing (with 16-bit index registers and long offset) allows data access over

section 0 and 1.

All the peripherals are memory mapped in the data space.

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